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AgeCommit message (Expand)Author
2015-07-30cpu: Fix drain issues in the Minor CPUAndreas Sandberg
2015-07-30mem: Add missing clean eviction on uncacheable accessAndreas Hansson
2015-07-30mem: Remove unused RequestCause in cacheAndreas Hansson
2015-07-30mem: Make caches way awareDavid Guillen-Fandos
2015-07-30mem: Transition away from isSupplyExclusive for writebacksAndreas Hansson
2015-07-30mem: Tidy up CacheBlk classAndreas Hansson
2015-07-30mem: Tidy up packetAndreas Hansson
2015-07-30cpu: Fix issue identified by UBSanAndreas Hansson
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-26cpu: o3: slight correction to identation in rename_impl.hhNilay Vaish
2015-07-24style: change Process function calls to use camelCaseBrandon Potter
2015-07-24syscall_emul: standardized file descriptor name and add return checks.Brandon Potter
2015-07-24base: refactor process class (specifically FdMap and friends)Brandon Potter
2015-07-24syscall_emul: file descriptor interface changesBrandon Potter
2015-07-24ruby: dma sequencer: removes redundant codeBrandon Potter
2015-07-22ruby: network: NetworkLink inherits from Consumer now.Nilay Vaish
2015-07-17x86: decode instructions with vex prefixNilay Vaish
2015-07-15dev: add support for multi gem5 runsGabor Dozsa
2015-07-13mem: Fix (ab)use of emplace to avoid temporary object creationAndreas Hansson
2015-07-13mem: Updated DRAMSim2 wrapper to new drain APIAndreas Hansson
2015-07-10ruby: replace global g_abs_controls with per-RubySystem varBrandon Potter
2015-07-10ruby: replace global g_system_ptr with per-object pointersBrandon Potter
2015-07-10ruby: replace g_ruby_start with per-RubySystem m_start_cycleBrandon Potter
2015-07-10ruby: remove extra whitespace and correct misspelled wordsBrandon Potter
2015-07-07dev, arm: Add a device model that uses the NoMali modelAndreas Sandberg
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07sim: Move mem(Writeback|Invalidate) to SimObjectAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-07python: Remove redundant drain when changing memory modesAndreas Sandberg
2015-07-07sim: Add macros to serialize objects into a sectionAndreas Sandberg
2015-07-07base: Add serialization support to Pixels and FrameBufferAndreas Sandberg
2015-07-07sim: Fix broken event unserializationAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-07-07sim: Add serialization macros for std containersAndreas Sandberg
2015-07-06mem: Cleanup CommMonitor in preparation for probe supportAndreas Sandberg
2015-07-04x86: Adjust the size of the values written to the x87 misc registersNikos Nikoleris
2015-07-04o3: correct the number of cc registers in rename mapNilay Vaish
2015-07-04mem: packet: Add const to constructor argumentNilay Vaish
2015-07-04ruby: drop NetworkMessage classNilay Vaish
2015-07-04ruby: mesi three level: name change to avoid clashNilay Vaish
2015-07-04ruby: remove message buffer nodeNilay Vaish
2015-07-03mem: Increase the default buffer sizes for the DDR4 controllerAndreas Hansson
2015-07-03mem: Update DRAM command scheduler for bank groupsWendy Elsasser
2015-07-03mem: Avoid DRAM write queue iteration for merging and read lookupAndreas Hansson
2015-07-03mem: Delay responses in the crossbar before forwardingAndreas Hansson
2015-07-03mem: Remove redundant is_top_level cache parameterAndreas Hansson
2015-07-03mem: Split WriteInvalidateReq into write and invalidateAndreas Hansson
2015-07-03mem: Add ReadCleanReq and ReadSharedReq packetsAndreas Hansson
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