| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-06-02 | ARM: Fix multiply overflow flag setting. | Gabe Black | |
| 2010-06-02 | ARM: Decode the saturation instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement the saturation instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement base classes for the saturation instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the signed add/subtract and subtract/add instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement signed add/subtract and subtract/add. | Gabe Black | |
| 2010-06-02 | ARM: Decode the unsigned 8 and 16 bit add and subtract instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement the unsigned 8 bit and 16 bit vector adds and subtracts. | Gabe Black | |
| 2010-06-02 | ARM: Decode the unsigned saturating instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement the unsigned saturating instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the ssub instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement the ssub instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the SADD8 and SADD16 instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement the SADD8 and SADD16 instructions. | Gabe Black | |
| 2010-06-02 | ARM: Support instructions that set the GE bits when they write the condition ↵ | Gabe Black | |
| codes. | |||
| 2010-06-02 | ARM: Decode 32 bit thumb data processing register instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the 16 bit thumb versions of the REV* instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the ARM version of the REV* instructions. | Gabe Black | |
| 2010-06-02 | ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions ↵ | Gabe Black | |
| into a format. | |||
| 2010-06-02 | ARM: Implement the REV* instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add base classes suitable for the REV* instructions. | Gabe Black | |
| 2010-06-02 | ARM: Make LDM that loads the PC perform an interworking branch. | Gabe Black | |
| 2010-06-02 | ARM: Decode the swp and swpb instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement the swp and swpb instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode MRS and MSR for thumb. | Gabe Black | |
| 2010-06-02 | ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones. | Gabe Black | |
| 2010-06-02 | ARM: Define versions of MSR and MRS outside the decoder. | Gabe Black | |
| 2010-06-02 | ARM: Hook up the push/pop versions of stm/ldm in thumb. | Gabe Black | |
| 2010-06-02 | ARM: Hook SVC into the thumb decoder. | Gabe Black | |
| 2010-06-02 | ARM: Implement SVC (was SWI) outside of the decoder. | Gabe Black | |
| 2010-06-02 | ARM: Trigger system calls from the SupervisorCall invoke method. | Gabe Black | |
| This simplifies the decoder slightly, and makes the system call mechanism very slightly more realistic. | |||
| 2010-06-02 | ARM: Fix multiply operations. | Gabe Black | |
| These fixes were provided by Ali and fix the saturation condition code and various multiply instructions. | |||
| 2010-06-02 | ARM: Decode the scalar saturating add/subtract instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the parallel add and subtract instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement signed saturating add and/or subtract instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implemented prefetch instructions/decoding (pli, pld, pldw). | Gabe Black | |
| 2010-06-02 | ARM: Decode unconditional ARM instructions. | Gabe Black | |
| 2010-06-02 | ARM: Make sure ldm exception return writes back its base in the right mode. | Gabe Black | |
| This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end. | |||
| 2010-06-02 | ARM: Rework how unrecognized/unimplemented instructions are handled. | Gabe Black | |
| Instead of panic immediately when these instructions are executed, an UndefinedInstruction fault is returned. In FS mode (not currently implemented), this is the fault that should, to my knowledge, be triggered in these situations and should be handled using the normal architected mechanisms. In SE mode, the fault causes a panic when it's invoked that gives the same information as the instruction did. When/if support for speculative execution of ARM is supported, this will allow a mispeculated and unrecognized and/or unimplemented instruction from causing a panic. Only once the instruction is going to be committed will the fault be invoked, triggering the panic. | |||
| 2010-06-02 | ARM: Add support for "SUBS PC, LR and related instructions". | Gabe Black | |
| 2010-06-02 | ARM: Make ldrs into the PC and ldm exception return do interworking branches. | Gabe Black | |
| 2010-06-02 | ARM: Align the PC when using it as the base for a load. | Gabe Black | |
| 2010-06-02 | ARM: Implement ADR as separate from ADD. | Gabe Black | |
| 2010-06-02 | ARM: Add support for interworking branch ALU instructions. | Gabe Black | |
| 2010-06-02 | ARM: Fix when the flag bits are updated for thumb. | Gabe Black | |
| 2010-06-02 | ARM: Don't rely on undefined behavior to get arithmetic right shift. | Gabe Black | |
| Shifting to the right of a signed value when the MSB is one is technically undefined behavior, even though in my experience it's done the "right thing" and sign extended the value. This replaces the arithmetic right shift code in ARM that uses that coincidence with some code that relies on bit math. | |||
| 2010-06-02 | ARM: Restrict the shift amount from a register to 8 bits. | Gabe Black | |
| The shift amount when taken from a register is supposed to be truncated to an 8 bit value. | |||
| 2010-06-02 | ARM: Define the VFP load/store multiple instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the VFP load/store multiple instructions. | Gabe Black | |
| 2010-06-02 | ARM: Fix the constant describing the number of floating point registers. | Gabe Black | |
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