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2008-03-22Fix cache problem with writes to tempBlockSteve Reinhardt
getting wrong writeback address. --HG-- extra : convert_revision : 023dfb69c227c13a69bfe2744c6af75a45828b0b
2008-03-20MIPS: Check endianness of binaries in SE mode.Gabe Black
--HG-- extra : convert_revision : e6c4bda6078eb68a26f8834411f744078c6bf5a9
2008-03-17Fix a few Packet memory leaks.Steve Reinhardt
--HG-- extra : convert_revision : 00db19f0698c0786f0dff561eea9217860a5a05a
2008-03-17Restructure bus timing calcs to cope with pkt being deleted by target.Steve Reinhardt
--HG-- extra : convert_revision : db8497e73a44f2a06aab121e797e88b4c0c31330
2008-03-15Fix subtle cache bug where read could return stale dataSteve Reinhardt
if a prior write miss arrived while an even earlier read miss was still outstanding. --HG-- extra : convert_revision : 4924e145829b2ecf4610b88d33f4773510c6801a
2008-03-06MergeGabe Black
--HG-- extra : convert_revision : ec5f41b2007ade15f6f4c4a1533e50f9cba2798e
2008-03-06X86: Refine the local APIC.Gabe Black
--HG-- extra : convert_revision : 2789c54ed555fed2f2a333fcc7dc6454f294ebf2
2008-03-06O3CPU: Don't call dumpInsts if DEBUG is not definedVilas Sridharan
--HG-- extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245
2008-03-01X86: Don't map the local APIC into the physical address space in SE mode.Gabe Black
--HG-- extra : convert_revision : b7103974b12130bbf43583c4cb5294b808add208
2008-02-27Automated merge with ssh://daystrom.m5sim.org//repo/m5Steve Reinhardt
--HG-- extra : convert_revision : f4bcd342e7abb86ca83840b723e6ab0b861ecf5b
2008-02-27Add comments in code to describe bug conditions.Korey Sewell
This should help if somebody gets to the bug fix before me (or someone else)... --HG-- extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
2008-02-27Fix Load/Store Queue squashing after a SMT thread is removed but ensuringKorey Sewell
you are squashing from the current instruction # causing the thread exit. --HG-- extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
2008-02-27Fix offset in removeThread() function so that float registers start freeing upKorey Sewell
from the right point (#32 usually) instead of restarting at 0 and double-freeing. Commented out assert line in free_list.hh that will check for when double-free condition goes bad. --HG-- extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
2008-02-26Revamp cache timing access mshr check to make stats sane again.Steve Reinhardt
--HG-- extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea
2008-02-27Configs: Make using Simpoints easier with some config files that support ↵Rick Strong
them easily --HG-- extra : convert_revision : 0f21829306eb68b332f03da410e6c341c8595bdd
2008-02-26X86: Put in initial implementation of the local APIC.Gabe Black
--HG-- extra : convert_revision : 1708a93d96b819e64ed456c75dbb5325ac8114a8
2008-02-26X86: Implement the INVLPG instruction and the TIA microop.Gabe Black
--HG-- extra : convert_revision : 31db1ee082f6c3ca5443cba1eb335e408661ead2
2008-02-26TLB: Make a TLB base class and put a virtual demapPage function in it.Gabe Black
--HG-- extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
2008-02-26X86: Get PCI config space to work, and adjust address space prefix numbering ↵Gabe Black
scheme. --HG-- extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
2008-02-26Cache: better comments particularly regarding writeback situation.Steve Reinhardt
--HG-- extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
2008-02-26Bus: Fix the bus timing to be more realistic.Gabe Black
--HG-- extra : convert_revision : acd70dc98ab840e55b114706fbb6afb2a95e54bc
2008-02-16Make L2+ caches allocate new block for writeback missesSteve Reinhardt
instead of forwarding down the line. --HG-- extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
2008-02-14CPU: move the PC Events code to a place where the code won't be executed ↵Ali Saidi
multiple times if an instruction faults. --HG-- extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
2008-02-11Update copyright datesAli Saidi
--HG-- extra : convert_revision : 547e7ddff6b8005a9eaad60970bc51984e84fcd1
2008-02-11Automated merge with file:/home/stever/hg/m5-origSteve Reinhardt
--HG-- extra : convert_revision : 86a55cd98a9704f756a70aa0cbd2820cf92c821d
2008-02-11EXTRAS now points to src instead of needing 'src' subdir.Steve Reinhardt
--HG-- extra : convert_revision : 8e7e4516ace8c7852eeea3c479bfd567839a8061
2008-02-10Bus: Only update port cache when there is an item to update it with.Nicolas Zea
--HG-- extra : convert_revision : 84848fd48bb9e6693a0518c862364142b1969aa8
2008-02-10IGbE: Fix a couple of bugs.Ali Saidi
--HG-- extra : convert_revision : a1f16bd82b6fbd5b6b5dc0f08b9e69858bea86ca
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
--HG-- extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
--HG-- rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62
2008-02-06Make the Event::description() a const functionStephen Hines
--HG-- extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
2008-02-05Add base ARM code to M5Stephen Hines
--HG-- extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
2008-02-05Cleaned up os.path imports a bit.Steve Reinhardt
--HG-- extra : convert_revision : ee75bf9abd249ab053e804739cc50972475cd5b6
2008-02-05Make EXTRAS work for SConsopts too.Steve Reinhardt
Requires pushing source files down into 'src' subdir relative to directory listed in EXTRAS. --HG-- extra : convert_revision : ca04adc3e24c60bd3e7b63ca5770b31333d76729
2008-01-23X86: Put an SMBios/DMI table in memory.Gabe Black
This is basically just the header right now, but there's an untested mechanism in place to fill out the table and make sure everything is updated correctly. --HG-- extra : convert_revision : c1610c0dfa211b7e0d091a04133695d84f500a1c
2008-01-23X86: Optomize the bit scanning instruction microassembly a little. More can ↵Gabe Black
be done. --HG-- extra : convert_revision : 3cf6e972f0e41e3529a633ecbb31289e1bd17f0f
2008-01-22X86: Implement and attach the BSR and BSF instructions.Gabe Black
--HG-- extra : convert_revision : be7e11980092e5d1baff0e05d4ec910305966908
2008-01-21X86: Fill out group17 in the decoder.Gabe Black
--HG-- extra : convert_revision : 66ab9c0fc3086f66e3d6d82d47964ecf406c3a8a
2008-01-21X86: Use the existing boot_osflags instead of duplicating it.Gabe Black
--HG-- extra : convert_revision : e04e438d7d261a61c52b946c23cd126ed648814a
2008-01-14The reason is that the event is supposed to put the instructions ready to ↵Ke Meng
execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. Signed-off by: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
2008-01-12X86: Redo the bit test instructions.Gabe Black
--HG-- extra : convert_revision : 433c2a9f3675ed02f3be5ce759a440f2686d2ccd
2008-01-12X86: Fix the wrmsr instruction.Gabe Black
--HG-- extra : convert_revision : 12bc7e71226ebafb8eedadf6a3db82929e15e722
2008-01-12X86: Make the effective segment base shadow the regular one, not the selector.Gabe Black
--HG-- extra : convert_revision : 498c7c16d664c784b196885b1f35c3c6386c9cfc
2008-01-12X86: Make the IO ports work using extra physical address lines. Add a serial ↵Gabe Black
port. --HG-- extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
2008-01-12X86: Fix the general IO instructions dataSize.Gabe Black
--HG-- extra : convert_revision : 9774a52cb6a8e7632d1b1dc0706e5791cc18d238
2008-01-06Temporary fix for ll/sc bug see flyspray task for more info:Geoffrey Blake
http://www.m5sim.org/flyspray/task/197 Signed-off by: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81
2008-01-02Add ReadRespWithInvalidate to handle multi-level coherence situationSteve Reinhardt
where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. --HG-- extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
2008-01-02Mark cache-to-cache MSHRs as downstreamPending when necessary.Steve Reinhardt
Don't mark upstream MSHR as pending if downstream MSHR is already in service. --HG-- extra : convert_revision : e1c135ff00217291db58ce8a06ccde34c403d37f
2008-01-02Don't DPRINTF in the middle of a PrintReq.Steve Reinhardt
--HG-- extra : convert_revision : 6358c014d14a19a34111c39827b05987507544bb
2008-01-02Bug fix: functional cache port now needs otherPort set.Steve Reinhardt
--HG-- extra : convert_revision : fb007df73a77535a5dba19341f7b0b32e8c99548
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