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AgeCommit message (Expand)Author
2013-11-01mem: Fixes for DRAM stats accountingAndreas Hansson
2013-11-01mem: Fix the LPDDR3 page sizeAndreas Hansson
2013-11-01mem: Adding stats for DRAM power calculationNeha Agarwal
2013-11-01mem: Unify request selection for read and write queuesNeha Agarwal
2013-11-01mem: Add a simple adaptive version of the open-page policyAndreas Hansson
2013-11-01mem: Just-in-time write scheduling in DRAM controllerNeha Agarwal
2013-11-01mem: Add tRRD as a timing parameter for the DRAM controllerAndreas Hansson
2013-11-01mem: Less conservative tRAS in DRAM configurationsAndreas Hansson
2013-11-01mem: Make tXAW enforcement less conservative and per rankAni Udipi
2013-11-01mem: Fix for 100% write threshold in DRAM controllerNeha Agarwal
2013-11-01mem: Pick the next DRAM request based on bank availabilityAndreas Hansson
2013-11-01mem: Use the same timing calculation for DRAM read and writeAni Udipi
2013-11-01mem: Fix DRAM bank occupancy for streaming accessAni Udipi
2013-11-01mem: Schedule time for DRAM event taking tRAS into accountAni Udipi
2013-11-01mem: Add tRAS parameter to the DRAM controller modelAni Udipi
2013-11-01sim: Clarify the difference between tracing and debuggingAndreas Hansson
2013-10-31ARM: add support for TEEHBR accessChander Sudanthi
2013-10-31dev: Add 'OSC' oscillator sys control reg support to VersatileExpressMatt Evans
2013-10-31dev: Add support for MSI-X and Capability Lists for ARM and PCI devicesGeoffrey Blake
2013-10-31dev: Fix race conditions in IDE device on newer kernelsGeoffrey Blake
2013-10-31base: Add support for ipv6 into inet.hh/inet.ccGeoffrey Blake
2013-10-31cpu: Construct ROB with cpu params struct instead of each variableFaissal Sleiman
2013-10-31config: Fix handling of parents for simobject vectorsGeoffrey Blake
2013-10-31sim: added option to serialize SimLoopExitEventDam Sunwoo
2013-10-31mem: Add "const" attribute to Packet gettersStephan Diestelhorst
2013-10-31mem: Add privilege info to request classPrakash Ramrakhyani
2013-10-31cpu: Fix O3 issuse with load+barrier instructions.Ali Saidi
2013-10-30ruby: set SenderMachine in messages of MOESI_CMP_directoryLluc Alvarez
2013-10-30ruby: Fixed a deadlock when restoring a checkpoint with garnetEmilio Castillo
2013-10-17mem: De-virtualise interfaces in the CoherentBusStephan Diestelhorst
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-17mem: Add PortID to QueuedMasterPort constructorSascha Bischoff
2013-10-17arm: Add a 'clear PPI' method to gic_pl390Matt Evans
2013-10-17config: Fix ommission of number base in ethernet address paramGeoffrey Blake
2013-10-17config: Fix for port references generated multiple timesGeoffrey Blake
2013-10-17dev: Add option to disable framebuffer .bmp dump in run folderDam Sunwoo
2013-10-17cpu: Removing an unused variable in renameFaissal Sleiman
2013-10-17cpu: Change IEW DPRINTF to use IEW debug flagFaissal Sleiman
2013-10-17cpu: Put in assertions to check for maximum supported LQ/SQ sizeFaissal Sleiman
2013-10-17arm: Accomodate function name changes in newer linux kernelsEric Van Hensbergen
2013-10-17arm: Fix a GIC mask register bugAli Saidi
2013-10-17cpu: Fix O3 uncacheable load that is replayed but misses the TLBAli Saidi
2013-10-17mem: Make MemoryAccess flag more verboseAli Saidi
2013-10-17build: Place proto output in the same directory, also for EXTRASAndreas Hansson
2013-10-17dev: Allow additional UART interrupts to be setAli Saidi
2013-10-16kvm: Fix latency calculation of IPR accessesAndreas Sandberg
2013-10-15ruby: eliminate non-determinism from ruby.stats outputSteve Reinhardt
2013-10-15arch/x86: add support for explicit CC register fileYasuko Eckert
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu/o3: clean up rename map and free listSteve Reinhardt