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2015-11-27base: Add support for changing output directoriesAndreas Sandberg
This changeset adds support for changing the simulator output directory. This can be useful when the simulation goes through several stages (e.g., a warming phase, a simulation phase, and a verification phase) since it allows the output from each stage to be located in a different directory. Relocation is done by calling core.setOutputDir() from Python or simout.setOutputDirectory() from C++. This change affects several parts of the design of the gem5's output subsystem. First, files returned by an OutputDirectory instance (e.g., simout) are of the type OutputStream instead of a std::ostream. This allows us to do some more book keeping and control re-opening of files when the output directory is changed. Second, new subdirectories are OutputDirectory instances, which should be used to create files in that sub-directory. Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se> [sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version] Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-08-10mem, cpu: Add assertions to snoop invalidation logicStephan Diestelhorst
This patch adds assertions that enforce that only invalidating snoops will ever reach into the logic that tracks in-order load completion and also invalidation of LL/SC (and MONITOR / MWAIT) monitors. Also adds some comments to MSHR::replaceUpgrades().
2015-07-19cpu: Fix LLSC atomic CPU wakeupKrishnendra Nathella
Writes to locked memory addresses (LLSC) did not wake up the locking CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU, recvAtomicSnoop was checking if the incoming packet was an invalidation (isInvalidate) and only then handled a locked snoop. But, writes are seen instead of invalidates when running without caches (fast-forward configurations). As as simple fix, now handleLockedSnoop is also called even if the incoming snoop packet are from writes.
2016-02-29arm: Squash after returning from exceptions in v7Mitch Hayenga
Properly done for the ERET instruction in v8, but not for v7. Many control register changes are only visible after explicit instruction synchronization barriers or exception entry/exit. This means mode changing instructions should squash any younger in-flight speculative instructions.
2016-02-29base: support gzip-compressed object filesCurtis Dunham
2016-02-24mem: Ensure that InvalidateReq is not forwarded as ReadExReqAndreas Hansson
This patch fixes an issue where an InvalidationReq only traversed one level of the cache hierarchy, and was subsequently turned into a ReadExReq due to it needing writable, and the command not being checked for explicitly.
2016-02-24cpu: TraceGen fix for tick frequency checkMatteo Andreozzi
Bug fix for check on protobuf file frequency being different than global frequency. The ASCII encoder script is also fixed, and the example trace used in the regressions is updated.
2016-02-23dev, arm: Implement the NoMali reset callbackAndreas Sandberg
Add a callback handler for the NoMali reset callback. This callback is called whenever the GPU is reset using the register interface or the NoMali API. The callback can be used to override ID registers using the raw register API.
2016-02-23dev, arm: Refactor the NoMali GPUAndreas Sandberg
Refactor and cleanup the NoMaliGpu class: * Use a std::map instead of a switch block to map the parameter enum describing the GPU type to a NoMali type. * Remove redundant NoMali handle from the interrupt callback. * Make callbacks and API wrappers protected instead of private to enable future extensions. * Wrap remaining NoMali API calls.
2016-02-23scons: Add missing override to appease clangAndreas Hansson
Make clang happy...again.
2016-02-18ruby: move range change send from RubyPort to derived classes.Tony Gutierrez
2016-02-18gpu: fix bugs with MemFence, Flat Instrs and Resource utilizationJohn Kalamatianos
Both Memory Fence is now flagged as Global Memory only to avoid resource oversubscribing. Flat instructions now check for Shared Memory resource busy to avoid oversubscribing resources. All WaitClass resources now use cycles (not ticks) to register the number of pipe stages between Scoreboard and Execute to be consistent with instruction scheduling logic which always used clock cycles.
2016-02-17gpu-compute: remove brig_object.hh from hsa_object.ccTony Gutierrez
brig_object.hh is specific to the HSAIL ISA, and hence should not be included in ISA-agnostic code.
2016-02-17ruby: send address ranges from RubyPortTony Gutierrez
2016-02-17scons: Enable building with the gcc/clang Address SanitizerAndreas Hansson
Allow the user to easily build gem5 with the Address Sanitizer, part of both gcc and clang these days.
2016-02-15misc: Add missing overrides to appease clangAndreas Hansson
Since the last round of fixes a few new issues have snuck in. We should consider switching the regression runs to clang.
2016-02-15mem: Avoid using invalid iterator in cache lock list traversalAndreas Hansson
Fix up issue highlighted by Valgrind and the clang Address Sanitizer.
2016-02-14ruby: make DMASequencer inherit from RubyPortMichael LeBeane
This patch essentially rolls back 10518:30e3715c9405 to make RubyPort the parent class of DMASequencer. It removes redundant code and restores some features which were lost when directly inheriting from MemObject. For example, DMASequencer can now communicate to other devices using PIO, which is useful for memmory-mapped communication between multiple DMADevices.
2016-02-13configs: add command-line option to stop debug outputMichael LeBeane
This patch adds a --debug-end flag to main.py so that debug output can be stoped at a specified tick, while allowing the simulation to continue. It is useful in situations where you would like to produce a trace for a region of interest while still collecting stats for the entire run. This is in contrast to the currently existing --debug-break flag, which terminates the simulation at the tick.
2016-02-13syscall_emul: Implement clock_getres() system callMichael LeBeane
This patch implements the clock_getres() system call for arm and x86 in linux SE mode.
2016-02-10mem: Be less conservative in clearing load locks in the cacheAndreas Hansson
Avoid being overly conservative in clearing load locks in the cache, and allow writes to the line if they are from the same context. This is in line with ALPHA and ARM.
2016-02-10mem: Move the point of coherency to the coherent crossbarAndreas Hansson
This patch introduces the ability of making the coherent crossbar the point of coherency. If so, the crossbar does not forward packets where a cache with ownership has already committed to responding, and also does not forward any coherency-related packets that are not intended for a downstream memory controller. Thus, invalidations and upgrades are turned around in the crossbar, and the memory controller only sees normal reads and writes. In addition this patch moves the express snoop promotion of a packet to the crossbar, thus allowing the downstream cache to check the express snoop flag (as it should) for bypassing any blocking, rather than relying on whether a cache is responding or not.
2016-02-10mem: Align cache behaviour in atomic when upstream is respondingAndreas Hansson
Adopt the same flow as in timing mode, where the caches on the path to memory get to keep the line (if present), and we use the responderHadWritable flag to determine if we need to forward the (invalidating) packet or not.
2016-02-10mem: Align how snoops are handled when hitting writebacksAndreas Hansson
This patch unifies the snoop handling in case of hitting writebacks with how we handle snoops hitting in the tags. As a result, we end up using the same optimisation as the normal snoops, where we inform the downstream cache if we encounter a line in Modified (writable and dirty) state, which enables us to avoid sending out express snoops to invalidate any Shared copies of the line. A few regressions consequently change, as some transactions are sunk higher up in the cache hierarchy.
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
This patch changes how the cache determines if snoops should be forwarded from the memory side to the CPU side. Instead of having a parameter, the cache now looks at the port connected on the CPU side, and if it is a snooping port, then snoops are forwarded. Less error prone, and less parameters to worry about. The patch also tidies up the CPU classes to ensure that their I-side port is not snooping by removing overrides to the snoop request handler, such that snoop requests will panic via the default MasterPort implement
2016-02-08scons: always generate sim/tags.ccCurtis Dunham
Due to insufficient build deps, the checkpoint tags might not get updated; this commit solves this. Due to the uncommon nature of the build target, regenerating tags.cc is a fairly clean solution. Since SCons hashes file contents, it won't recompile anything unless a new checkpoint upgrader is actually added. --HG-- extra : amend_source : ed3879da7668554693f697076deaf5029cc9b954
2016-02-06x86: revamp cmpxchg8b/cmpxchg16b implementationAlexandru Dutu
The previous implementation did a pair of nested RMW operations, which isn't compatible with the way that locked RMW operations are implemented in the cache models. It was convenient though in that it didn't require any new micro-ops, and supported cmpxchg16b using 64-bit memory ops. It also worked in AtomicSimpleCPU where atomicity was guaranteed by the core and not by the memory system. It did not work with timing CPU models though. This new implementation defines new 'split' load and store micro-ops which allow a single memory operation to use a pair of registers as the source or destination, then uses a single ldsplit/stsplit RMW pair to implement cmpxchg. This patch requires support for 128-bit memory accesses in the ISA (added via a separate patch) to support cmpxchg16b.
2016-02-06arch, x86: add support for arrays as memory operandsSteve Reinhardt
Although the cache models support wider accesses, the ISA descriptions assume that (for the most part) memory operands are integer types, which makes it difficult to define instructions that do memory accesses larger than 64 bits. This patch adds some generic support for memory operands that are arrays of uint64_t, and specifically a 'u2qw' operand type for x86 that is an array of 2 uint64_ts (128 bits). This support is unused at this point, but will be needed shortly for cmpxchg16b. Ideally the 128-bit SSE memory accesses will also be rewritten to use this support. Support for 128-bit accesses could also have been added using the gcc __int128_t extension, which would have been less disruptive. However, although clang also supports __int128_t, it's still non-standard. Also, more importantly, this approach creates a path to defining 256- and 512-byte operands as well, which will be useful for eventual AVX support.
2016-02-06arch: get rid of dummy var initSteve Reinhardt
MemOperand variables were being initialized to 0 "to avoid 'uninitialized variable' errors" but these no longer seem to be a problem (with the exception of one use case in POWER that is arguably broken and easily fixed here). Getting rid of the initialization is necessary to set up a subsequent patch which extends memory operands to possibly not be scalars, making the '= 0' initialization no longer feasible.
2016-02-06syscall_emul: fix bug in aux vector initializationSteve Reinhardt
Writing 16 bytes from an 8-byte source value is a bad idea. This doesn't appear to have broken anything, but showed up as spurious differences when tracediffing runs.
2016-02-06style: eliminate explicit boolean comparisonsSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-control -a' to get rid of '== true' comparisons, plus trivial manual edits to get rid of '== false'/'== False' comparisons. Left a couple of explicit comparisons in where they didn't seem unreasonable: invalid boolean comparison in src/arch/mips/interrupts.cc:155 >> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<< invalid boolean comparison in src/unittest/unittest.hh:110 >> "EXPECT_FALSE(" #expr ")", (expr) == false)<<
2016-02-06x86: create function to check miscreg validitySteve Reinhardt
In the process of trying to get rid of an '== false' comparison, it became apparent that a slightly more involved solution was needed. Split this out into its own changeset since it's not a totally trivial local change like the others.
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-control -a'.
2016-02-06style: remove trailing whitespaceSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-white -a'.
2016-02-06dist, dev: add an ethernet switch modelMohammad Alian
2016-01-22ruby: removed Write_Only AccessPermissionBrad Beckmann
2015-07-20ruby: split CPU and GPU latency statsDavid Hashe
2016-01-19gpu-compute: AMD's baseline GPU modelTony Gutierrez
2016-01-19mem: write combining for ruby protocolsTony Gutierrez
This patch adds support for write-combining in ruby.
2016-01-19* * *Tony Gutierrez
mem: support for gpu-style RMWs in ruby This patch adds support for GPU-style read-modify-write (RMW) operations in ruby. Such atomic operations are traditionally executed at the memory controller (instead of through an L1 cache using cache-line locking). Currently, this patch works by propogating operation functors through the memory system.
2015-07-20mem: misc flags for AMD gpu modelBlake Hechtman
This patch add support to mark memory requests/packets with attributes defined in HSA, such as memory order and scope.
2016-01-17sim: fix redundant --debug-start help stringSteve Reinhardt
Just changes the metavar for --debug-start from TIME to TICK in cset 72046b9b3323 and didn't notice that the comment "must be in ticks" is now redundant.
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
For historical reasons, the ExecContext interface had a single function, readMem(), that did two different things depending on whether the ExecContext supported atomic memory mode (i.e., AtomicSimpleCPU) or timing memory mode (all the other models). In the former case, it actually performed a memory read; in the latter case, it merely initiated a read access, and the read completion did not happen until later when a response packet arrived from the memory system. This led to some confusing things, including timing accesses being required to provide a pointer for the return data even though that pointer was only used in atomic mode. This patch splits this interface, adding a new initiateMemRead() function to the ExecContext interface to replace the timing-mode use of readMem(). For consistency and clarity, the readMemTiming() helper function in the ISA definitions is renamed to initiateMemRead() as well. For x86, where the access size is passed in explicitly, we can also get rid of the data parameter at this level. For other ISAs, where the access size is determined from the type of the data parameter, we have to keep the parameter for that purpose.
2016-01-17cpu: remove unnecessary data ptr from O3 internal read() funcsSteve Reinhardt
The read() function merely initiates a memory read operation; the data doesn't arrive until the access completes and a response packet is received from the memory system. Thus there's no need to provide a data pointer; its existence is historical. Getting this pointer out of this internal o3 interface sets the stage for similar cleanup in the ExecContext interface. Also found that we were pointlessly setting the contents at this pointer on a store forward (the useful memcpy happens just a few lines below the deleted one).
2016-01-17arch: don't call *Timing functions from *Atomic versionsSteve Reinhardt
The readMemAtomic/writeMemAtomic helper functions were calling readMemTiming/writeMemTiming respectively. This is functionally correct, since the *Timing functions are doing the same access initiation operation as the *Atomic functions (just that the *Atomic versions also complete the access in line). It also provides for some (very minimal) code reuse. Unfortunately, it's potentially pretty confusing, since it makes it look like the atomic accesses are somehow being converted to timing accesses. It also gets in the way of specializing the timing interface (as will be done in a future patch).
2016-01-17arch: get rid of unused LargestRead typedefSteve Reinhardt
2016-01-17sim: don't ignore SIG_TRAPSteve Reinhardt
By ignoring SIG_TRAP, using --debug-break <N> when not connected to a debugger becomes a no-op. Apparently this was intended to be a feature, though the rationale is not clear. If we don't ignore SIG_TRAP, then using --debug-break <N> when not connected to a debugger causes the simulation process to terminate at tick N. This is occasionally useful, e.g., if you just want to collect a trace for a specific window of execution then you can combine this with --debug-start to do exactly that. In addition to not ignoring the signal, this patch also updates the --debug-break help message and deletes a handful of unprotected calls to Debug::breakpoint() that relied on the prior behavior.
2016-01-15dev, arm: Add a platform with support for both aarch32 and aarch64Andreas Sandberg
Add a platform with support for both aarch32 and aarch64. This platform implements a subset of the devices in a real Versatile Express and extends it with some gem5-specific functionality. It is in many ways similar to the old VExpress_EMM64 platform, but supports the following new features: * Automatic PCI interrupt assignment * PCI interrupts allocated in a contiguous range. * Automatic boot loader selection (32-bit / 64-bit) * Cleaner memory map where gem5-specific devices live in CS5 which isn't used by current Versatile Express platforms. * No fake devices. Devices that were previously faked will be removed from the device tree instead. * Support for 510 GiB contiguous memory
2016-01-15dev, arm: Add support for automatic PCI interrupt routingAndreas Sandberg
Add support for automatic PCI interrupt routing using a device's ID on the PCI bus. Our current DTBs typically tell the kernel that we do this or something similar when declaring the PCI controller. This changeset adds an option to make the simulator behave in the same way. Interrupt routing can be selected by setting the int_policy parameter in the GenericArmPciHost. The following values are supported: * ARM_PCI_INT_STATIC: Use the old static routing policy using the interrupt line from a device's configurtion space. * ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an interrupt in the GIC. The interrupt is computed as: gic_int = int_base + (pci_dev % int_count) * ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to an interrupt in the GIC. The PCI specification reserves pin ID 0 for devices without interrupts, the interrupt therefore computed as: gic_int = int_base + ((pin - 1) % int_count)
2016-01-11mem: fix bug in packet access endianness changesSteve Reinhardt
The new Packet::setRaw() method incorrectly still contained an htog() conversion. As a result, calls to the old set() method (now defined as setRaw(htog(v))) underwent two htog conversions, which breaks things when htog() is not a no-op. Interestingly the only test that caught this was a SPARC boot test, where an IsaFake device with a non-zero return value was getting swapped twice resulting in a register getting loaded with 0x100000000000000 instead of 1. (Good reason for keeping SPARC around, perhaps?)