gem5 - gem5

Age	Commit message (Expand)	Author
2012-08-21	Device: Remove overloaded pio_latency parameter	Andreas Hansson
2012-08-21	CPU: Remove overloaded function_trace_start parameter	Andreas Hansson
2012-08-21	PacketQueue: Allow queuing in the same tick as desired send tick	Andreas Hansson
2012-08-21	EventManager: Remove test for NULL pointer in constructor	Andreas Hansson
2012-08-21	Clock: Make Tick unsigned and remove UTick	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-08-19	Ruby Banked Array: add copyrights	Nilay Vaish
2012-08-16	Ruby: Add RubySystem parameter to MemoryControl	Jason Power
2012-08-16	Alpha System: override startup(), instead of loadState()	Nilay Vaish
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-08-15	sysemul: bump all linux versions of for syscal emulation to 3.0.	Ali Saidi
2012-08-10	Ruby: Clean up topology changes	Jason Power
2012-08-08	System: set kernel to null, if unspecified.	Nilay Vaish
2012-08-06	syscall emulation: Enabled getrlimit and getrusage for x86.	Marc Orr
2012-08-06	SETranslatingPortProxy: fix bug in tryReadString()	Steve Reinhardt
2012-08-06	process: add progName() virtual function	Steve Reinhardt
2012-08-06	syscall_emul: clean up open() code a bit.	Steve Reinhardt
2012-08-06	str: add an overloaded startswith() utility method	Steve Reinhardt
2012-08-06	syscall emulation: Clean up ioctl handling, and implement for x86.	Marc Orr
2012-08-01	Ruby NetDest: add assert for bad element in netdest	Jason Power
2012-07-27	dma: remove unused variable	Anthony Gutierrez
2012-07-27	checker: make checker cpu id match its host's cpu id	Anthony Gutierrez
2012-07-27	cache: don't allow dirty data in the i-cache	Anthony Gutierrez
2012-07-27	ARM: fix value of MISCREG_CTR returned by readMiscReg()	Anthony Gutierrez
2012-07-23	Bridge: Use EventWrapper instead of Event subclass for sendEvent	Andreas Hansson
2012-07-22	X86 CPUID: Return false if unknown processor family	Nilay Vaish
2012-07-12	Mem: Make SimpleMemory single ported	Andreas Hansson
2012-07-12	Ruby: remove config information from ruby.stats	Nilay Vaish
2012-07-12	Ruby: remove some unused stuff from SLICC files	Nilay Vaish
2012-07-11	x86: added page size in bytes tlb entry function	Brad Beckmann
2012-07-11	ruby: improved DRAM reset comment	Brad Beckmann
2012-07-10	syscall emulation: Add the futex system call.	Marc Orr
2012-07-10	x86: logSize and lruSeq are now optional ckpt params	Brad Beckmann
2012-07-10	Add hook to call map() on Process from python.	Steve Reinhardt
2012-07-10	# User Brad Beckmann <Brad.Beckmann@amd.com>	Brad Beckmann
2012-07-10	ruby: remove the cpu assumptions for the random tester	Brad Beckmann
2012-07-10	# User Brad Beckmann <Brad.Beckmann@amd.com>	Brad Beckmann
2012-07-10	imported patch jason/slicc-external-structure-fix	Brad Beckmann
2012-07-10	ruby: banked cache array resource model	Brad Beckmann
2012-07-10	ruby: tag and data cache access support	Joel Hestness
2012-07-10	ruby: adds reset function to Ruby memory controllers	Nuwan Jayasena
2012-07-10	ruby: memory controllers now inherit from an abstract "MemoryControl" class	Nuwan Jayasena
2012-07-10	cpu: added assertions to ensure the correct proxies are used	Brad Beckmann
2012-07-10	ruby: changes how Topologies are created	Brad Beckmann
2012-07-09	EventManager: Rename queue accessor and remove cast operator	Andreas Hansson
2012-07-09	Mem: Make members relating to range and size constant	Andreas Hansson
2012-07-09	Port: Hide the queue implementation in SimpleTimingPort	Andreas Hansson
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Bus: Make the default bus width 8 bytes instead of 64	Andreas Hansson
2012-07-09	Bus: Split the bus into separate request/response layers	Andreas Hansson