Age | Commit message (Collapse) | Author |
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into multiple memory access.
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counted.
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extra : convert_revision : 9ef81afcfabd86c9c069204998c987344f03f33e
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It should be cleared prior to the call to recvRetry.
Add extra DPRINTF statement for clearer debugging output.
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parameters.
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extra : convert_revision : 765b096785a77df9adc4791c9101b90696bd7be2
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In O3, a nop is used to carry faults down the pipeline that didn't originate
from an instruction. If the instruction doesn't do anything, that is just
returns NoFault, but doesn't have IsNop set, the NoFault will overwrite the
fault that's being sent down and nothing will happen.
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extra : convert_revision : 54d99002b550ca0e1cf14603f588dc1038e3e535
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doesn't cause a false branch mispredict.
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extra : convert_revision : 2820597cc966cd7b128cef0dab48fe05089533d7
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Each "strand" may need to have a private copy of this state, but I couldn't
find anywhere in the spec that said that after looking briefly.
This prevents writes to the thread context in o3 which was causing the
pipeline to be flushed and stopping any forward progress. The other ASI
accessible state will probably need to be accessed differently if/when we get
O3 full system up and running.
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extra : convert_revision : fa7fba812d7f76564ef4a23818e60f536710d557
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No_Fault ASI accesses work.
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extra : convert_revision : 3c480537bf38f74f0f1d72e75c70aa46ba91b759
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import sys since sys may not be defined in whatever context the DictImporter
is used. Also reset self.installed after an unload since the same DictImporter
could be used again
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extra : convert_revision : 988ed7ad8cd41b69e8fc583e618b1b4a146216da
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extra : convert_revision : 31aad7170b35556a4c984f4ebc013137d55d85eb
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Lets CPU accesses to physical memory bypass Bus.
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extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
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simple-timing test for ALPHA_FS breaks.
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extra : convert_revision : 5a1b05cddd480849913da81a3b3931fec16485a8
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way so a cache can handle partial block requests for i/o devices.
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Improve MRU checking for StaticInst, Bus, TLB
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extra : convert_revision : 663021070a4bcc795bb44e1839b8bcec686a42f0
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Fixed the asz assembler symbol.
Adjusted the condion checks to have appropriate options.
Implemented the SCAS microcode.
Attached SCAS into the decoder.
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extra : convert_revision : 17bf9ddae6bc2069e43b076f8f83c4e54fb7966c
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repne prefixes.
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Also some touch up for ruflag.
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There is a fundemental flaw in how unaligned accesses are supported, but this
is still an improvement.
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REX prefix.
The only cases where this was the correct behavior are now handled with the
"B" operand type, and doing things this way was breaking some instructions,
notably a shift.
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Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
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extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
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This lets you index into a group of registers without having to know
explicitly which one is the lowest in that group.
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extra : convert_revision : e3cad25a1c5910955204c37177b049ca9834cfd9
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The arch_prctl system call is used to set and get the FS and GS segment
bases. The FS segment is use for TLS, so glibc needs to be able to set it
up.
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This allows us to change memory modes as well.
Clean up the code while we're at it.
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(instead of %import)
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This requires us to not use PyRun_SimpleString, but PyRun_String since the
latter actually returns a result
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--HG--
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