Age | Commit message (Collapse) | Author |
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conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic
src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata
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extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
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that made ccprintf and friends work, turn it into a
normal function (though it still has a slightly strange
implementation.) All instances of variadic macros
are not yet removed, but I know how, and it will happen.
One side effect of this new implementation is that a
cprintf statement can now only have 16 parameters, though
it's easy enough to raise this number if needed.
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extra : convert_revision : 85cb3c17f8e2ecf9cd2f31ea80a760a28ea127a7
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to a stream compared to sprintf to a buffer.
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extra : convert_revision : de80724943d18aa110aa39cde9414252d9a7944c
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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into zeep.pool:/z/saidi/work/m5.newmem
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into vm1.(none):/home/stever/bk/newmem-head
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extra : convert_revision : c2350e01a052114a264f26551b13fca03a835c61
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Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.
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fix unaligned accesses in mmaped disk device
src/arch/sparc/isa/decoder.isa:
get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
move the cexec into the aexec field
src/cpu/exetrace.cc:
copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
fix unaligned accesses in the memory mapped disk device
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extra : convert_revision : aaa33096b08cf0563fe291d984a87493a117e528
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definition as well as the declaration.
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in debugging mode (especially valuable for tracediff).
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extra : convert_revision : 227434a06b5271a8300f2f6861bd06c4ac19e6c4
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src/arch/sparc/isa/decoder.isa:
fix rdgsr fault check
src/arch/sparc/tlb.cc:
block asis are now supported
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extra : convert_revision : cf55d648d2c5184fab03b6fe057d0e33c1dfc393
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src/arch/sparc/floatregfile.cc:
fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
fix printing of float registers
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extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
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into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
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src/SConscript:
strip doesn't take a src and dest in solaris
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into zeep.pool:/z/saidi/work/m5.newmem
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src/arch/sparc/floatregfile.cc:
Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
fix serialization for intreg
src/arch/sparc/miscregfile.cc:
fix serialization from miscreg
src/arch/sparc/pagetable.cc:
fix serialization for page table
src/arch/sparc/regfile.cc:
need to serialize nnpc
src/arch/sparc/tlb.cc:
write serialization code for tlb
src/cpu/base.cc:
provide a way to find the thread number a context is
serialize the instruction counter
src/cpu/base.hh:
provide a way to find the thread number a context is
and given a thread number find a context pointer
src/cpu/cpuevent.hh:
provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
Make findObj() work (it hasn't since we did the python conversion stuff)
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extra : convert_revision : a95bc4e3c3354304171efbe3797556fdb146bea2
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 7b332ee4c737206511d26db391117eb1fe5ea290
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src/arch/sparc/isa/base.isa:
Added passesFpCondition function to help with fbfcc and fbpfcc instructions.
src/arch/sparc/isa/decoder.isa:
Added fbfcc and fbpfcc instructions, and cleaned up branch code slightly.
src/arch/sparc/isa/formats/branch.isa:
Minor cleanup.
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extra : convert_revision : 6586b46418f1f70bace41407f267fee30c657714
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way to do this.
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of the pointer, not the memory.
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setSingleStep
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unimplemented floating point ops.
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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right with respect to quite NaNs, but hopefully we don't need to worry about the distinction.
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into zeep.pool:/z/saidi/work/m5.newmem
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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into zeep.pool:/z/saidi/work/m5.newmem
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into pb15.local:/Users/ali/work/m5.newmem.head
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extra : convert_revision : b4db0b350c8a5b3452ede74e5b42eec8ed6685c3
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return correct traps for ua2005 fpops that aren't implemented in hw
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : f25fd4855a1eaaecb29e6ccc3cee22cf07e4108b
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make fp writes also chatty with the Sparc traceflag
src/arch/sparc/floatregfile.cc:
make fp writes also chatty with the Sparc traceflag
src/cpu/exetrace.cc:
fix comparing fp registers between legion and m5
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extra : convert_revision : f3703afae56249f137451262bc1b6919d465e714
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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