Age | Commit message (Collapse) | Author |
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
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we can merge back with newmem.
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/sparc/miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
fix for build
src/cpu/exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
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extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
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fix namespace indentations
src/arch/alpha/tlb.cc:
fix namespace indentations
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extra : convert_revision : 327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
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still use some work.
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extra : convert_revision : f79f863393f918ff9363b2c261f8c0dfec64312e
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fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
src/arch/sparc/asi.cc:
flesh out twinx asis
src/arch/sparc/miscregfile.cc:
fix TICK register reads
src/arch/sparc/tlb.cc:
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
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extra : convert_revision : 1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress
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extra : convert_revision : d420ee86454b72b0e5d3a98bac3b496f172c1788
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Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
fix bug in tlb map code
src/base/range_map.hh:
fix bug in rangemap code and add range_multimap
(these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
fix up the rangemap unit test to catch the missing case
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extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
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the oldest instruction is passed on to commit).
This fixes a minor bug when multiple FU completions come back out of order (due to the order in which the FUs are freed up), and the oldest redirect isn't recorded properly. The eon benchmark should run now.
src/cpu/o3/iew_impl.hh:
Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
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extra : convert_revision : b7d202dee1754539ed814f0fac59adb8c6328ee1
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(read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
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extra : convert_revision : a8030132268662ca54f487b8d32d09ba224317a8
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there was a fault prior to translation).
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extra : convert_revision : 43f4ea5e6a234cc6071006eab72135c11b8523c8
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extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : e1ed5c8edb95e99200b4d26317f55f71338a96df
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extra : convert_revision : d25604156ae0b2cf29d92fb960b8f5d77427985b
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : c51fd95f7acd7cffb3ea705d7216772f0a801844
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Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
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extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge
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extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
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src/arch/sparc/interrupts.hh:
add in thread_context.hh to get access to tc.
get rid of stubs that don't make sense right now.
implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.
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extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
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src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices
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extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
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Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
Handle access to ASI_QUEUE
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extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
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getting touched.
configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request
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extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
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extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43
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extra : convert_revision : c2ede9efbf7b264c32d5565d3f0fc0601c4cd63b
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into zower.eecs.umich.edu:/eecshome/m5/newmemmid
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extra : convert_revision : 45d9599dd883e10c283812c1c241c20323f44cec
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extra : convert_revision : 4a985635cda7680abcddaf0bc9579fa03d5bc7c6
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file (reducing the number of if FULL_SYSTEM defines and includes)
Protect other pieces of code so that sparc compiles SE again
src/arch/sparc/SConscript:
Add ua2005.cc back into SConscript
src/arch/sparc/miscregfile.hh:
add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness
src/arch/sparc/mmaped_ipr.hh:
wrap handleIpr* with if full_system so it compiles under se
src/arch/sparc/ua2005.cc:
reorganize edit fs only miscreg functions
src/cpu/exetrace.cc:
protect legion code so it doesn't try to compile under se
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extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76
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correctly
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extra : convert_revision : 60fef1bd5dc03d7b107150dba922dd4a3f51626f
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instead of template parameter.
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extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
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configs/common/FSConfig.py:
seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
Use instruction count from cpu rather than cycles because that is what legion does
we can change it back after were done with legion
src/base/bitfield.hh:
add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
change asserts of packet success to if panics wrapped with NDEBUG defines
so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
convert some tabs to spaces
src/python/m5/objects/T1000.py:
add more fake devices for each l1 bank and each memory controller
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extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : 321f7fcc8bd6c6aaaab92d10172814f4d07d5e65
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extra : convert_revision : 2ccb75b0912a384789458710fd9bbb65626f839e
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extra : convert_revision : 520814e193b9e86b6410f3ab98d62ed131d295aa
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instead of a template policy.
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extra : convert_revision : 6a4ac7a189a950390a973fdfce94f56190de92db
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make sure these changes (commit especially) work okay.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch_impl.hh:
Fixes for MIPS_SE compile.
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extra : convert_revision : fde9616f8e72b397c5ca965774172372cff53790
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get symbols for where it's copied to in memory
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it
configs/common/FSConfig.py:
We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
Let kernel be none
src/sim/system.cc:
Let the system kernel be none, but warn about it
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extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
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fix addr alignment problem
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into zower.eecs.umich.edu:/eecshome/m5/newmemmid
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
hand merge
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extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : c358d5e3211756bbf905eef2a62b65a2e56a86f3
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src/arch/SConscript:
add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits
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extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
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below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.
Right now this introduces a minor memory leak as old physPorts and virtPorts are not deleted when new ones are created. A flyspray task has been created for this issue. It can not be resolved until we determine how the bus will handle giving out ID's to functional ports that may be deleted.
src/cpu/o3/cpu.cc:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Change the setup of the physPort and virtPort to instead happen every time the CPU has a context activated. This is a little high overhead, but keeps it working correctly when the CPU does not have a physical memory attached to it until it switches in (like the case of switch CPUs).
src/cpu/o3/thread_context.hh:
Change function from being called at init() to just being called whenever the memory ports need to be connected.
src/cpu/o3/thread_context_impl.hh:
Update this to not delete the port if it's the same as the virtPort.
src/cpu/thread_context.hh:
Change function from being called at init() to whenever the memory ports need to be connected.
src/cpu/thread_state.cc:
Instead of initializing the ports, simply connect them, deleting any old ports that might exist. This allows these functions to be called multiple times.
src/cpu/thread_state.hh:
Ports are no longer initialized, but rather connected at context activation time.
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extra : convert_revision : e399ce5dfbd6ad658c953a7c9c7b69b89a70219e
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress
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extra : convert_revision : ffc7931d7da153b421b3c838a0968e484fd182ec
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cache is used in a uniprocessor setting.
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extra : convert_revision : 020a9799cd7177fdb85a767701d6fcb8cf018827
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extra : convert_revision : ebda49bff30d76d3209acce55458d3f4e29594d3
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src/arch/sparc/process.cc:
MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
Sparc version of this file.
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extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
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into ewok.(none):/home/gblack/m5/newmemo3
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extra : convert_revision : e8d6ce19a83fe526112c1dd61c48196eb8c0951f
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 7dbd30ce5579dd62d5f54bb5d75cf12346bc5d1d
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