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AgeCommit message (Expand)Author
2010-06-02ARM: Move the VFP data operation decode into a function.Gabe Black
2010-06-02ARM: Implement and update the DFSR and IFSR registers on faults.Gabe Black
2010-06-02ARM: Make integer division by zero return a fault.Gabe Black
2010-06-02ARM: Add in some missing SCTLR fields.Gabe Black
2010-06-02ARM: Decode ARM unconditional MRC and MCR instructions.Gabe Black
2010-06-02ARM: Move the CP15 decode block into a function.Gabe Black
2010-06-02ARM: Decode the unconditional version of ARM fp instructions.Gabe Black
2010-06-02ARM: Move the FP decode blocks into functions.Gabe Black
2010-06-02ARM: Warn/ignore when TLB maintenance operations are performed.Gabe Black
2010-06-02ARM: Handle accesses to TLBTR.Gabe Black
2010-06-02ARM: Handle accesses to the DACR.Gabe Black
2010-06-02ARM: Handle accesses to TTBR0 and TTBR1.Gabe Black
2010-06-02ARM: Convert the CP15 registers from MPU to MMU.Gabe Black
2010-06-02ARM: Add some support for wfi/wfe/yield/etcAli Saidi
2010-06-02ARM: Move PC mode bits around so they can be used for exectraceAli Saidi
2010-06-02ARM: Add a traceflag to print cpsrAli Saidi
2010-06-02ARM: Undef instruction on invalid user CP15 accessAli Saidi
2010-06-02ARM: Decode the VSTR instruction.Gabe Black
2010-06-02ARM: Implement the vstr instruction.Gabe Black
2010-06-02ARM: BXJ should be BX when there is no J supportAli Saidi
2010-06-02ARM: Make sure macroops aren't interrupted midinstruction.Gabe Black
2010-06-02ARM: Fix the implementation of the VFP ldm and stm macroops.Gabe Black
2010-06-02Simple CPU: Make the FloatRegs trace flag do something.Gabe Black
2010-06-02ARM: Fix up thumb decoding of coproc instructions.Gabe Black
2010-06-02ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR,...Gabe Black
2010-06-02CPU: Reset fetch offset after a exceptionAli Saidi
2010-06-02ARM: Decode the VLDR instruction.Gabe Black
2010-06-02ARM: Implement the VLDR instruction.Gabe Black
2010-06-02ARM: Decode all the various forms of vmov.Gabe Black
2010-06-02ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.Gabe Black
2010-06-02ARM: Implement the various versions of VMOV.Gabe Black
2010-06-02ARM: Add a new RegImmOp base class.Gabe Black
2010-06-02ARM: Add a RegRegImmOp base class.Gabe Black
2010-06-02ARM: Widen the immediate fields in the misc instruction classes.Gabe Black
2010-06-02ARM: Add a function to decode VFP modified immediate constants.Gabe Black
2010-06-02ARM: Add a function to decode SIMD modified immediate constants.Gabe Black
2010-06-02ARM: Add fp operands to operands.isa.Gabe Black
2010-06-02ARM: Decode the VMRS instruction.Gabe Black
2010-06-02ARM: Update the set of FP related miscregs.Gabe Black
2010-06-02ARM: Implement the VMRS instruction.Gabe Black
2010-06-02ARM: Decode the VMSR instruction.Gabe Black
2010-06-02ARM: Implement the VMSR instruction.Gabe Black
2010-06-02ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) regis...Gabe Black
2010-06-02ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.Gabe Black
2010-06-02ARM: Implement the udiv instruction.Gabe Black
2010-06-02ARM: Implement the sdiv instruction.Gabe Black
2010-06-02ARM: Ignore writing a bad mode to CPSR with MSR.Gabe Black
2010-06-02ARM: Decode the CPS instruction.Gabe Black
2010-06-02ARM: Implement the CPS instruction.Gabe Black
2010-06-02ARM: Decode the SRS instruction.Gabe Black