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2012-05-30Packet: Unify the use of PortID in packet and portAndreas Hansson
This patch removes the Packet::NodeID typedef and unifies it with the Port::PortId. The src and dest fields in the packet are used to hold a port id (e.g. in the bus), and thus the two should actually be the same. The typedef PortID is now global (in base/types.hh) and aligned with the ThreadID in terms of capitalisation and naming of the InvalidPortID constant. Before this patch, two flags were used for valid destination and source, rather than relying on a named value (InvalidPortID), and this is now redundant, as the src and dest field themselves are sufficient to tell whether the current value is a valid port identifier or not. Consequently, the VALID_SRC and VALID_DST are removed. As part of the cleaning up, a number of int parameters and local variables are updated to use PortID. Note that Ruby still has its own NodeID typedef. Furthermore, the MemObject getMaster/SlavePort still has an int idx parameter with a default value of -1 which should eventually change to PortID idx = InvalidPortID.
2012-05-30Packet: Updated comments for src and dest fieldsAndreas Hansson
This patch updates the comments for the src and dest fields to reflect their actual use. Due to a number of patches (e.g. removing the Broadcast flag), the old comments are no longer indicative of the current usage.
2012-05-30Bridge: Split deferred request, response and sender stateAndreas Hansson
This patch splits the PacketBuffer class into a RequestState and a DeferredRequest and DeferredResponse. Only the requests need a SenderState, and the deferred requests and responses only need an associated point in time for the request and the response queue. Besides the cleaning up, the goal is to simplify the transition to a new port handshake, and with these changes, the two packet queues are starting to look very similar to the generic packet queue, but currently they do a few unique things relating to the NACK and counting of requests/responses that the packet queue cannot be conveniently used. This will be addressed in a later patch.
2012-05-28X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB.Gabe Black
2012-05-27X86: Move the GDT down to where it can be accessed in 32 bit mode.Gabe Black
The GDT can be accessed by user level software running in compatibility mode by moving segment selectors into segment registers. The GDT needs to be set up at an address accessible in this mode.
2012-05-27X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode.Gabe Black
A small change was added a while ago to keep addresses from overflowing 32 bits when larger addresses shouldn't be accessible to software. That change truncated when not in long mode, but really it should have truncated when not in 64 bit mode. The difference is whether compatibility mode is included, a mode that's supposed to act like a legacy 32 bit mode.
2012-05-26ISA,CPU: Generalize and split out the components of the decode cache.Gabe Black
This will allow it to be specialized by the ISAs. The existing caching scheme is provided by the BasicDecodeCache in the GenericISA namespace and is built from the generalized components. --HG-- rename : src/cpu/decode_cache.cc => src/arch/generic/decode_cache.cc
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
These classes are always used together, and merging them will give the ISAs more flexibility in how they cache things and manage the process. --HG-- rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc
2012-05-25ISA: Make the decode function part of the ISA's decoder.Gabe Black
2012-05-25CPU: Simplify the implementation of the decode cache.Gabe Black
Also reorganize it to make it more amenable to being rearranged later.
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
--HG-- rename : src/cpu/decode.cc => src/arch/generic/decoder.cc rename : src/cpu/decode.hh => src/arch/generic/decoder.hh
2012-05-24Cache: Remove dangling doWriteback declarationAndreas Hansson
This patch removes the declaration of doWriteback as there is no implementation for this member function.
2012-05-23Packet: Cleaning up packet command and attributeAndreas Hansson
This patch removes unused commands and attributes from the packet to avoid any confusion. It is part of an effort to clear up how and where different commands and attributes are used.
2012-05-23Config: Use the attribute naming and include ports in JSONAndreas Hansson
This patch changes the organisation of the JSON output slightly to make it easier to traverse and use the files. Most importantly, the hierarchical dictionaries now use keys that correspond to the attribute names also in the case of VectorParams (used to be e.f. "cpu0 cpu1"). It also adds the name and the path to each SimObject directory entry. Before this patch, to get cpu0, you would have to query dict['system']['cpu0 cpu1'][0] and this could be a dict with 'cpu0' : { cpu parameters }. Now you use dict['system']['cpu'][0] and get { cpu parameters } (where one is "name" : "cpu0"). Additionally this patch includes more verbose information about the ports, specifying their role, and using a JSON array rather than a concatenated string for the peer.
2012-05-23DMA: Split the DMA device and IO device into seperate filesAndreas Hansson
This patch moves the DMA device to its own set of files, splitting it from the IO device. There are no behavioural changes associated with this patch. The patch also grabs the opportunity to do some very minor tidying up, including some white space removal and pruning some redundant parameters. Besides the immediate benefits of the separation-of-concerns, this patch also makes upcoming changes more streamlined as it split the devices that are only slaves and the DMA device that also acts as a master. --HG-- rename : src/dev/io_device.cc => src/dev/dma_device.cc rename : src/dev/io_device.hh => src/dev/dma_device.hh
2012-05-23MEM: Add a snooping DMA port subclass for table walkerAndreas Hansson
This patch makes the (device) DmaPort non-snooping and removes the recvSnoop constructor parameter and instead introduces a SnoopingDmaPort subclass for the ARM table walker. Functionality is unchanged, as are the stats, and the patch merely clarifies that the normal DMA ports are not snooping (although they may issue requests that are snooped by others, as done with PCI, PCIe, AMBA4 ACE etc). Currently this port is declared in the ARM table walker as it is not used anywhere else. If other ports were to have similar behaviour it could be moved in a future patch.
2012-05-23Config: Exit with fatal if a port is already connectedAndreas Hansson
This patch turns the existing warning into a fatal, as there should never be any cases where a (non-vector) port is assigned to and then later connected to something else. If this behaviour is allowed, as it used to be, there are cases where the wrong number of C++ ports are created when instantiating objects with VectorPorts (obviously that could be fixed, but the better approach is to simply not allow it).
2012-05-22Ruby: Remove the unused src/mem/ruby/common/Driver.* files.Nilay Vaish
2012-05-22Ruby Sequencer: Schedule deadlock check event at correct timeNilay Vaish
The scheduling of the deadlock check event was being done incorrectly as the clock was not being multiplied, so as to convert the time into ticks. This patch removes that bug.
2012-05-22X86: Split Condition Code registerNilay Vaish
This patch moves the ECF and EZF bits to individual registers (ecfBit and ezfBit) and the CF and OF bits to cfofFlag registers. This is being done so as to lower the read after write dependencies on the the condition code register. Ultimately we will have the following registers [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Note that this is only one part of the solution for lowering the dependencies. The other part will check whether or not the condition code register needs to be actually read. This would be done through a separate patch.
2012-05-19x86 ISA: Implement the sse3 haddps instruction.Marc Orr
Shuffle the 32 bit values into position, and then add in parallel.
2012-05-19Syscalls: warn when the length argument to mmap is excessive.Gabe Black
If the length argument to mmap is larger than the arbitrary but reasonable limit of 4GB, there's a good chance that the value is nonsense and not intentional. Rather than attempting to satisfy the mmap anyway, this change makes gem5 warn to make it more apparent what's going wrong.
2012-05-14Mem: Fix size check when allocating physical memoryLena Olson
2012-05-10ARM: fix the calculation of the values in the RV clocksKoan-Sin Tan
This clock is used by the linux scheduler.
2012-05-10stats: fix compilation of unit test.Ali Saidi
2012-05-10stats: fix bug in assert for 2d vectorAli Saidi
2012-05-10ARM: pl011 raw interrupt fixChander Sudanthi
Raw interrupt was not being set when interrupt was disabled. This patch sets the raw interrupt regardless of the mask.
2012-05-10ARM: EMM board address range fixChander Sudanthi
0x40000000 is reservered for external AXI addresses. This address range is not used currently. Removed the range from the bridge.
2012-05-10DOT: improved dot-based system visualizationUri Wiener
Revised system visualization to reflect structure and memory hierarchy. Improved visualization: less congested and cluttered; more colorful. Nodes reflect components; directed edges reflect dirctional relation, from a master port to a slave port. Requires pydot.
2012-05-10DOT: fixed broken code for visualizing configuration using dotUri Wiener
Fixed broken code which visualizes the system configuration by generating a tree from each component's children, starting from root. Requires DOT (hence pydot).
2012-05-10ARM: guard masked symbol tables by defaultDam Sunwoo
Symbol tables masked with the loadAddrMask create redundant entries that could conflict with kernel function events that rely on the original addresses. This patch guards the creation of those masked symbol tables by default, with an option to enable them when needed (for early-stage kernel debugging, etc.)
2012-05-10mem: fix bug with CopyStringOut and null string termination.Ali Saidi
2012-05-10Cache: restructure code that actually isn't a loopAli Saidi
2012-05-10dev: use correct delete operation in SimpleDiskAli Saidi
2012-05-10ARM: Fix incorrect use of not operators in arm devicesAli Saidi
2012-05-10gem5: assert before indexing intro arrays to verify boundsAli Saidi
2012-05-10gem5: fix some iterator use and erase bugsAli Saidi
2012-05-10gem5: fix a number of use after free issuesAli Saidi
2012-05-10base: fix a invalid ?: operatorAli Saidi
2012-05-10gem5: Fix a number of incorrect case statementsAli Saidi
2012-05-10stats: track if the stats have been enabled and prevent requesting master idAli Saidi
Track the point in the initialization where statistics have been registered. After this point registering new masterIds can no longer work as some SimObjects may have sized stats vectors based on the previous value. If someone tries to register a masterId after this point the simulator executes fatal().
2012-05-10Cache: Panic if you attempt to create a checkpoint with a cache in the systemAli Saidi
2012-05-10IGbE: Fix writeback conditions for i8254x GbE in updated data sheet.Pritha Ghoshal
An older revision of the data sheet specified that txdctl.gran was 1 the granularity was based on cache block and gran being 0 is based on descriptor count. The newer version of the data sheet reverses this errata
2012-05-09stats: use nan instead of no_valueNathan Binkert
2012-05-09MEM: Add the communication monitorAndreas Hansson
This patch adds a communication monitor MemObject that can be inserted between a master and slave port to provide a range of statistics about the communication passing through it. The communication monitor is non-invasive and does not change any properties or timing of the packets, with the exception of adding a sender state to be able to track latency. The statistics are only collected in timing mode (not atomic) to avoid slowing down any fast forwarding. An example of the statistics captured by the monitor are: read/write burst lengths, bandwidth, request-response latency, outstanding transactions, inter transaction time, transaction count, and address distribution. The monitor can be used in combination with periodic resetting and dumping of stats (through schedStatEvent) to study the behaviour over time. In future patches, a selection of convenience scripts will be added to aid in visualising the statistics collected by the monitor.
2012-05-08MEM: Do not forward uncacheable to bus snoopersAndreas Hansson
This patch adds a guarding if-statement to avoid forwarding uncacheable requests (or rather their corresponding request packets) to bus snoopers. These packets should never have any effect on the caches, and thus there is no need to forward them to the snoopers.
2012-05-04Ruby: Ensure snoop requests are sent using sendTimingSnoopReqAndreas Hansson
This patch fixes a bug that caused snoop requests to be placed in a packet queue. Instead, the packet is now sent immediately using sendTimingSnoopReq, thus bypassing the packet queue and any normal responses waiting to be sent.
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
This patch moves send/recvTiming and send/recvTimingSnoop from the Port base class to the MasterPort and SlavePort, and also splits them into separate member functions for requests and responses: send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq, send/recvTimingSnoopResp. A master port sends requests and receives responses, and also receives snoop requests and sends snoop responses. A slave port has the reciprocal behaviour as it receives requests and sends responses, and sends snoop requests and receives snoop responses. For all MemObjects that have only master ports or slave ports (but not both), e.g. a CPU, or a PIO device, this patch merely adds more clarity to what kind of access is taking place. For example, a CPU port used to call sendTiming, and will now call sendTimingReq. Similarly, a response previously came back through recvTiming, which is now recvTimingResp. For the modules that have both master and slave ports, e.g. the bus, the behaviour was previously relying on branches based on pkt->isRequest(), and this is now replaced with a direct call to the apprioriate member function depending on the type of access. Please note that send/recvRetry is still shared by all the timing accessors and remains in the Port base class for now (to maintain the current bus functionality and avoid changing the statistics of all regressions). The packet queue is split into a MasterPort and SlavePort version to facilitate the use of the new timing accessors. All uses of the PacketQueue are updated accordingly. With this patch, the type of packet (request or response) is now well defined for each type of access, and asserts on pkt->isRequest() and pkt->isResponse() are now moved to the appropriate send member functions. It is also worth noting that sendTimingSnoopReq no longer returns a boolean, as the semantics do not alow snoop requests to be rejected or stalled. All these assumptions are now excplicitly part of the port interface itself.
2012-04-29X86: Fix the IMUL_R_P_I macroop.Gabe Black
The disp displacement was left off the load microop so the wrong value was used.
2012-04-29X86: Fix up the open system call's flags.Vince Weaver