gem5 - gem5

Age	Commit message (Expand)	Author
2012-11-02	mem: fix use after free issue in memories until 4-phase work complete.	Ali Saidi
2012-11-02	mem: Add support for writing back and flushing caches	Andreas Sandberg
2012-11-02	sim: Add drain methods to request additional cleanup operations	Andreas Sandberg
2012-11-02	sim: Add SWIG interface for Serializable	Andreas Sandberg
2012-11-02	python: Rename doDrain()->drain() and make it do the right thing	Andreas Sandberg
2012-11-02	sim: Reuse the code to change memory mode.	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	cpu: O3 add a header declaring the DerivO3CPU	Andreas Sandberg
2012-11-02	cpu: Add header files for checker CPUs	Andreas Sandberg
2012-11-02	dev: Fix ethernet device inheritance structure	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-11-02	pci: Make Python wrapper cast to the right type	Andreas Sandberg
2012-11-02	mips: Remove unused Python file	Andreas Sandberg
2012-11-02	dev: Add missing inline declarations	Andreas Sandberg
2012-11-02	base: Add missing header file to addr_range.hh.	Andreas Sandberg
2012-11-02	ARM: dump stats and process info on context switches	Dam Sunwoo
2012-11-02	base: Fix a few incorrectly handled print format cases	Chander Sudanthi
2012-11-02	base: split out the VncServer into a VncInput and Server classes	Chander Sudanthi
2012-11-02	ISA: generic Linux thread info support	Dam Sunwoo
2012-11-02	sim: Fix as issue where exit events on instr queues are used after freed.	Ali Saidi
2012-11-02	o3: Fix a couple of issues with the local predictor.	Mrinmoy Ghosh
2012-11-02	Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming	Andreas Sandberg
2012-10-31	mem: Fix typo in port comments	Andreas Hansson
2012-10-25	dev: Make default clock more reasonable for system and devices	Andreas Hansson
2012-10-25	arm: Use table walker clock that is inherited from CPU	Andreas Hansson
2012-10-23	dev: Remove zero-time loop in DMA timing send	Andreas Hansson
2012-10-18	ruby: functional access updates to network test protocol	Nilay Vaish
2012-10-15	ruby: improved support for functional accesses	Nilay Vaish
2012-10-15	memtest: move check on outstanding requests	Nilay Vaish
2012-10-15	ruby: register multiple memory controllers	Nilay Vaish
2012-10-15	ruby: remove AbstractMemOrCache	Nilay Vaish
2012-10-15	ruby: allow function definition in slicc structs	Nilay Vaish
2012-10-15	ruby banked array: do away with event scheduling	Nilay Vaish
2012-10-15	ruby: reset timing after cache warm up	Nilay Vaish
2012-10-15	Mem: Fix incorrect logic in bus blocksize check	Andreas Hansson
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Mem: Separate the host and guest views of memory backing store	Andreas Hansson
2012-10-15	Checkpoint: Make system serialize call children	Andreas Hansson
2012-10-15	Mem: Use deque instead of list for bus retries	Andreas Hansson
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-10-15	Regression: Use CPU clock and 32-byte width for L1-L2 bus	Andreas Hansson
2012-10-15	Clock: Inherit the clock from parent by default	Andreas Hansson
2012-10-15	Param: Fix proxy traversal to support chained proxies	Andreas Hansson
2012-10-15	Mem: Use range operations in bus in preparation for striping	Andreas Hansson
2012-10-11	Mem: Determine bus block size during initialisation	Andreas Hansson
2012-10-11	Doxygen: Update the version of the Doxyfile	Andreas Hansson
2012-10-02	ruby: makes some members non-static	Nilay Vaish
2012-10-02	ruby: changes to simple network	Nilay Vaish
2012-10-02	ruby: rename template_hack to template	Nilay Vaish