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2011-01-07scons: show sources and targets when building, and colorize output.Steve Reinhardt
I like the brevity of Ali's recent change, but the ambiguity of sometimes showing the source and sometimes the target is a little confusing. This patch makes scons typically list all sources and all targets for each action, with the common path prefix factored out for brevity. It's a little more verbose now but also more informative. Somehow Ali talked me into adding colors too, which is a whole 'nother story.
2011-01-04Ruby: Updates MOESI Hammer protocolNilay Vaish
This patch changes the manner in which data is copied from L1 to L2 cache in the implementation of the Hammer's cache coherence protocol. Earlier, data was copied directly from one cache entry to another. This has been broken in to two parts. First, the data is copied from the source cache entry to a transaction buffer entry. Then, data is copied from the transaction buffer entry to the destination cache entry. This has been done to maintain the invariant - at any given instant, multiple caches under a controller are exclusive with respect to each other.
2011-01-04Params: Print the IP components in the right order.Gabe Black
2011-01-03Move sched_list.hh and timebuf.hh from src/base to src/cpu.Steve Reinhardt
These files really aren't general enough to belong in src/base. This patch doesn't reorder include lines, leaving them unsorted in many cases, but Nate's magic script will fix that up shortly. --HG-- rename : src/base/sched_list.hh => src/cpu/sched_list.hh rename : src/base/timebuf.hh => src/cpu/timebuf.hh
2011-01-03Delete unused files from src/base directory.Steve Reinhardt
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
2011-01-03RefCount: Fix reference counting pointer == and != with a T* on the left.Gabe Black
These operators were expecting a const T& instead of a const T*, and were not being picked up and used by gcc in the right places as a result. Apparently no one used these operators before. A unit test which exposed these problems, verified the solution, and checks other basic functionality is on the way.
2010-12-30swig: use <> for system %includes instead of ""Nathan Binkert
2010-12-23PerfectCacheMemory: Add return statements to two functions.Nilay Vaish
Two functions in src/mem/ruby/system/PerfectCacheMemory.hh, tryCacheAccess() and cacheProbe(), end with calls to panic(). Both of these functions have return type other than void. Any file that includes this header file fails to compile because of the missing return statement. This patch adds dummy values so as to avoid the compiler warnings.
2010-12-22This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh ↵Nilay Vaish
file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh
2010-12-21memtest: delete some crufty dead codeSteve Reinhardt
2010-12-21Get rid of unused file src/base/dbl_list.hhSteve Reinhardt
2010-12-21stats: allow stats to be reset even if no objects have been instantiatedNathan Binkert
2010-12-21importer: fix error messageNathan Binkert
2010-12-21scons: remove extra dependenciesNathan Binkert
2010-12-20Style: Replace some tabs with spaces.Gabe Black
2010-12-20Params: Fix a broken error message in verifyIp.Gabe Black
2010-12-09ARM: Take advantage of new PCState syntax.Gabe Black
2010-12-09ARM: Get rid of some unused FP operands.Gabe Black
2010-12-08Merge.Gabe Black
2010-12-08ruby: remove Ruby asserts for m5.fastBrad Beckmann
This diff is for changing the way ASSERT is handled in Ruby. m5.fast compiles out the assert statements by using the macro NDEBUG. Ruby uses the macro RUBY_NO_ASSERT to do so. This macro has been removed and NDEBUG has been put in its place.
2010-12-08Alpha: Take advantage of new PCState syntax.Gabe Black
2010-12-08MIPS: Take advantage of new PCState syntax.Gabe Black
2010-12-08POWER: Take advantage of new PCState syntax.Gabe Black
2010-12-08SPARC: Take advantage of new PCState syntax.Gabe Black
2010-12-08X86: Take advantage of new PCState syntax.Gabe Black
2010-12-07ISA: Get the parser to support pc state components more elegantly.Gabe Black
2010-12-07O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).Ali Saidi
The store queue doesn't need to be ISA specific and architectures can frequently store more than an int registers worth of data. A 128 bits seems more common, but even 256 bits may be appropriate. Pretty much anything less than a cache line size is buildable.
2010-12-07O3: Support squashing all state after special instructionAli Saidi
For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply marking the instruction as Serializing isn't enough beacuse that only stops rename. This provides a mechanism to squash all the instructions and refetch them
2010-12-07O3: Make all instructions that write a misc. register not perform the write ↵Giacomo Gabrielli
until commit. ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-12-07ARM: Support switchover with hardware table walkersAli Saidi
2010-12-01ruby: Converted old ruby debug calls to M5 debug callsNilay Vaish
This patch developed by Nilay Vaish converts all the old GEMS-style ruby debug calls to the appropriate M5 debug calls.
2010-11-26IGbE: return 0 on an invalid descriptor size instead of -1.Ali Saidi
Asserts where descSize() get called with assert if we end up returning 0.
2010-11-23Copyright: Add AMD copyright to the param changes I just made.Gabe Black
2010-11-23Params: Add parameter types for IP addresses in various forms.Gabe Black
New parameter forms are: IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255. IP address with netmask which is an IP followed by "/n" where n is a netmask length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from decimal 0 to 255 and which is all 1 bits followed by all 0 bits when represented in binary. These can also be specified as an integral IP and netmask passed in separately. IP address with port which is an IP followed by ":p" where p is a port index from decimal 0 to 65535. These can also be specified as an integral IP and port value passed in separately.
2010-11-23X86: Loosen an assert for x86 and connect the APIC ports when caches are used.Gabe Black
2010-11-23X86: Obey the PCD (cache disable) bit in the page tables.Gabe Black
2010-11-22X86: Mark IO space accesses as uncachable.Gabe Black
2010-11-22IDE,X86: Fix IDE controller BAR configuration for x86.Gabe Black
2010-11-20random: small comment about our random number generator and its originNathan Binkert
2010-11-19SE: Fix simulating more than 4GB of RAM in SE modeAli Saidi
This change removes some dead code in PhysicalMemory, uses a 64 bit type for the page pointer in System (instead of 32 bit) and cleans up some style.
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-18O3: Fix fp destination register flattening, and index offset adjusting.Gabe Black
This change makes O3 flatten floating point destination registers, and also fixes misc register flattening so that it's correctly repositioned relative to the resized regions for integer and floating point indices. It also fixes some overly long lines.
2010-11-15O3: Make O3 support variably lengthed instructions.Gabe Black
2010-11-15O3: reset architetural state by calling clear()Ali Saidi
2010-11-15ARM: Add comment about the organization of the IT state registerAli Saidi
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15O3: prevent a squash when completeAcc() modifies misc reg through TC.Min Kyu Jeong
This happens on ARM instructions when they update the IT state bits. Code and associated comment was copied from execute() and initiateAcc() methods
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is ↵Ali Saidi
accessed. Just panicing in readMiscReg() doesn't work because a speculative access in the o3 model can end the simulation.