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2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
This patch introduces port access methods that separates snoop request/responses from normal memory request/responses. The differentiation is made for functional, atomic and timing accesses and builds on the introduction of master and slave ports. Before the introduction of this patch, the packets belonging to the different phases of the protocol (request -> [forwarded snoop request -> snoop response]* -> response) all use the same port access functions, even though the snoop packets flow in the opposite direction to the normal packet. That is, a coherent master sends normal request and receives responses, but receives snoop requests and sends snoop responses (vice versa for the slave). These two distinct phases now use different access functions, as described below. Starting with the functional access, a master sends a request to a slave through sendFunctional, and the request packet is turned into a response before the call returns. In a system without cache coherence, this is all that is needed from the functional interface. For the cache-coherent scenario, a slave also sends snoop requests to coherent masters through sendFunctionalSnoop, with responses returned within the same packet pointer. This is currently used by the bus and caches, and the LSQ of the O3 CPU. The send/recvFunctional and send/recvFunctionalSnoop are moved from the Port super class to the appropriate subclass. Atomic accesses follow the same flow as functional accesses, with request being sent from master to slave through sendAtomic. In the case of cache-coherent ports, a slave can send snoop requests to a master through sendAtomicSnoop. Just as for the functional access methods, the atomic send and receive member functions are moved to the appropriate subclasses. The timing access methods are different from the functional and atomic in that requests and responses are separated in time and send/recvTiming are used for both directions. Hence, a master uses sendTiming to send a request to a slave, and a slave uses sendTiming to send a response back to a master, at a later point in time. Snoop requests and responses travel in the opposite direction, similar to what happens in functional and atomic accesses. With the introduction of this patch, it is possible to determine the direction of packets in the bus, and no longer necessary to look for both a master and a slave port with the requested port id. In contrast to the normal recvFunctional, recvAtomic and recvTiming that are pure virtual functions, the recvFunctionalSnoop, recvAtomicSnoop and recvTimingSnoop have a default implementation that calls panic. This is to allow non-coherent master and slave ports to not implement these functions.
2012-04-14Regression: Add ANSI colours to highlight test statusAndreas Hansson
This patch adds a very basic pretty-printing of the test status (passed or failed) to highlight failing tests even more: green for passed, and red for failed. The printing only uses ANSI it the target output is a tty and supports ANSI colours. Hence, any regression scripts that are outputting to files or sending e-mails etc should still be fine.
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
This patch addresses a number of minor issues that cause problems when compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it avoids using the deprecated ext/hash_map and instead uses unordered_map (and similarly so for the hash_set). To make use of the new STL containers, g++ and clang has to be invoked with "-std=c++0x", and this is now added for all gcc versions >= 4.6, and for clang >= 3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1 unordered_map to avoid the deprecation warning. The addition of c++0x in turn causes a few problems, as the compiler is more stringent and adds a number of new warnings. Below, the most important issues are enumerated: 1) the use of namespaces is more strict, e.g. for isnan, and all headers opening the entire namespace std are now fixed. 2) another other issue caused by the more stringent compiler is the narrowing of the embedded python, which used to be a char array, and is now unsigned char since there were values larger than 128. 3) a particularly odd issue that arose with the new c++0x behaviour is found in range.hh, where the operator< causes gcc to complain about the template type parsing (the "<" is interpreted as the beginning of a template argument), and the problem seems to be related to the begin/end members introduced for the range-type iteration, which is a new feature in c++11. As a minor update, this patch also fixes the build flags for the clang debug target that used to be shared with gcc and incorrectly use "-ggdb".
2012-04-13SCons: restore Werror option in src/SConscriptSteve Reinhardt
Partial backout of cset 8b223e308b08. Although it's great that there's currently no need for Werror=false in the current tree, some of us have uncommitted code that still needs this option.
2012-04-12Ruby: Ensure order-dependent iteration uses an ordered mapAndreas Hansson
This patch fixes a bug in Ruby that caused non-deterministic simulation when changing the underlying hash map implementation. The reason is order-dependent behaviour in combination with iteration over the hash map contents. The two locations where a sorted container is assumed are now changed to make use of a std::map instead of the unordered hash map. With this change, the stats changes slightly and the follow-on changeset will update the relevant statistics.
2012-04-09tests: Fix building unit tests.Gabe Black
Unit tests shouldn't build in gem5's main function because they have thier own.
2012-04-06rubytest: remove spurious printfBrad Beckmann
2012-04-06slicc: Controllers attached to Sequencers no longer have to be named L1Cache.Lisa Hsu
2012-04-06sim-ruby: checkpointing fixes and dependent eventq improvementsBrad Beckmann
Fixes checkpointing with respect to lost events after swapping event queues. Also adds DPRINTFs to better understand what's going on when Ruby serializes and unserializes.
2012-04-06slicc: fixed error message when the type has no inheritanceBrad Beckmann
2012-04-06MOESI_hammer: tbe allocation and dependent wakeup fixesBrad Beckmann
2012-04-06python: added __nonzero__ function to SimObject Bool paramsBrad Beckmann
2012-04-06MOESI_hammer: fixed bug with single cpu + flushes, then modified the ↵Brad Beckmann
regression tester to check this functionality
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
This patch allows the ruby tester to support protocols where the i-cache and d-cache are managed by seperate controllers.
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. --HG-- rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py rename : src/mem/physical.cc => src/mem/abstract_mem.cc rename : src/mem/physical.hh => src/mem/abstract_mem.hh rename : src/mem/physical.cc => src/mem/simple_mem.cc rename : src/mem/physical.hh => src/mem/simple_mem.hh
2012-04-05NetworkTest: remove unnecessary memory allocationTushar Krishna
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
With recent changes to the memory system, a port cannot be assigned a peer port twice. While making use of the Ruby memory system in FS mode, DMA ports were assigned peer twice, once for the classic memory system and once for the Ruby memory system. This patch removes this double assignment of peer ports.
2012-04-05Python: Make the All proxy traverse SimObject children as wellAndreas Hansson
This patch changes the behaviour of the All proxy parameter to not only consider the direct children, but also do a pre-order depth-first traversal of the object tree and append all results from the children. This is used in a later patch to find all the memories in the system, independent of where they are located in the hierarchy.
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
This patch removes the physmem_port from the Atomic CPU and instead uses the system pointer to access the physmem when using the fastmem option. The system already keeps track of the physmem and the valid memory address ranges, and with this patch we merely make use of that existing functionality. As a result of this change, the overloaded getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
2012-03-31X86: Fix address size handling so real mode works properly.Gabe Black
Virtual (pre-segmentation) addresses are truncated based on address size, and any non-64 bit linear address is truncated to 32 bits. This means that real mode addresses aren't truncated down to 16 bits after their segment bases are added in.
2012-03-30MEM: Remove legacy DRAM in preparation for memory updatesAndreas Hansson
This patch removes the DRAM memory class in preparation for updates to the memory system, with the first one introducing an abstract memory class, and removing the assumption of a single physical memory.
2012-03-30Ruby: Remove the physMemPort and instead access memory directlyAndreas Hansson
This patch removes the physMemPort from the RubySequencer and instead uses the system pointer to access the physmem. The system already keeps track of the physmem and the valid memory address ranges, and with this patch we merely make use of that existing functionality. The memory is modified so that it is possible to call the access functions (atomic and functional) without going through the port, and the memory is allowed to be unconnected, i.e. have no ports (since Ruby does not attach it like the conventional memory system).
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
2012-03-30CPU: Unify initMemProxies across CPUs and simulation modesAndreas Hansson
This patch unifies where initMemProxies is called, in the init() method of each BaseCPU subclass, before TheISA::initCPU is called. Moreover, it also ensures that initMemProxies is called in both full-system and syscall-emulation mode, thus unifying also across the modes. An additional check is added in the ThreadState to ensure that initMemProxies is only called once.
2012-03-26range_map: Enable const find and iterationAndreas Hansson
This patch adds const access functions to the range_map to enable its use in a const context, similar to the STL container classes.
2012-03-26Power: Change bitfield name to avoid conflicts with range_mapAndreas Hansson
This patch changes the name of a bitfield from W to W_FIELD to avoid clashes with W being used as a class (typename) in the templatized range_map. It also changes L to L_FIELD to avoid future problems. The problem manifestes itself when the CPU includes a header that in turn includes range_map.hh. The relevant parts of the decoder are updated.
2012-03-23Ruby: Fix Set::print for 32-bit hostsAndreas Hansson
This patch fixes a compilation error caused by a length mismatch on 32-bit hosts. The ifdef and sprintf is replaced by a csprintf.
2012-03-22MEM: Unify bus access methods and prepare for master/slave splitAndreas Hansson
This patch unifies the recvFunctional, recvAtomic and recvTiming to all be based on a similar structure: 1) extract information about the incoming packet, 2) send it out to the appropriate snoopers, 3) determine where it is going, and 4) forward it to the right destination. The naming of variables across the different access functions is now consistent as well. Additionally, the patch introduces the member functions releaseBus and retryWaiting to better distinguish between the two cases when we should tell a sender to retry. The first case is when the bus goes from busy to idle, and the second case is when it receives a retry from a destination that did not immediatelly accept a packet. As a very minor change, the MMU debug flag is no longer used in the bus.
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
This patch decouples the queueing and the port interactions to simplify the introduction of the master and slave ports. By separating the queueing functionality from the port itself, it becomes much easier to distinguish between master and slave ports, and still retain the queueing ability for both (without code duplication). As part of the split into a PacketQueue and a port, there is now also a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The QueuedPort is useful for ports that want to leave the packet transmission of outgoing packets to the queue and is used by both master and slave ports. The SimpleTimingPort inherits from the QueuedPort and adds the implemention of recvTiming and recvFunctional through recvAtomic. The PioPort and MessagePort are cleaned up as part of the changes. --HG-- rename : src/mem/tport.cc => src/mem/packet_queue.cc rename : src/mem/tport.hh => src/mem/packet_queue.hh
2012-03-22Scons: Remove Werror=False in SConscript filesAndreas Hansson
This patch removes the overriding of "-Werror" in a handful of cases. The code compiles with gcc 4.6.3 and clang 3.0 without any warnings, and thus without any errors. There are no functional changes introduced by this patch. In the future, rather than ypassing "-Werror", address the warnings.
2012-03-21Python: Fix a conditional expression that requires Python 2.5Andreas Hansson
This patch changes a conditional expression to a conventional if/else block, which does not require Python >= 2.5.
2012-03-21ARM: Fix case where cond/uncond control is mis-specifiedNathanael Premillieu
2012-03-21ARM: Clean up condCodes in IT blocks.Ali Saidi
2012-03-21ARM: IT doesn't need to be serializing.Geoffrey Blake
2012-03-21O3: Fix sizing of decode to rename skid buffer.Andrew Lukefahr
2012-03-21ARM: Add RTC to PBX SystemKoan-Sin Tan
2012-03-21O3: Fix size of skid buffer between fetch and decode when widths are differentBrian Grayson
2012-03-21ARM: Fix uninitialized value in ARM RTC model.Ali Saidi
2012-03-19Garnet: Stats at vnet granularity + code cleanupTushar Krishna
This patch (1) Moves redundant code from fixed and flexible networks to BaseGarnetNetwork. (2) Prints network stats at vnet granularity.
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
2012-03-19clang: Fix recently introduced clang compilation errorsAndreas Hansson
This patch makes the code compile with clang 2.9 and 3.0 again by making two very minor changes. Firt, it maintains a strict typing in the forward declaration of the BaseCPUParams. Second, it adds a FullSystemInt flag of the type unsigned int next to the boolean FullSystem flag. The FullSystemInt variable can be used in decode-statements (expands to switch statements) in the instruction decoder.
2012-03-19scripts: Fix to ensure that port connection count is always setAndreas Hansson
This patch ensures that the port connection count is set to zero in those cases when the port is not connected.
2012-03-11O3: Add fatal when fetchWidth > Impl::MaxWidth.Brian Grayson
2012-03-09ARM: Fix branch prediction issue with CB(N)Z instructionBrian Grayson
2012-03-09O3/Ozone: Eliminate dead code counting software prefetch instsGeoffrey Blake
Eliminates dead code in the O3 and Ozone CPU models that counted software prefetch instructions separately for the ALPHA ISA only.
2012-03-09CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPUGeoffrey Blake
Making the CheckerCPU a runtime time option requires the code to be compatible with ISAs other than ARM. This patch adds the appropriate function stubs to allow compilation.
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
2012-03-09ARM: Don't reset CPUs that are going to be switched in.Ali Saidi
2012-03-09System: Move code in initState() back into constructor whenever possible.Ali Saidi
The change to port proxies recently moved code out of the constructor into initState(). This is needed for code that loads data into memory, however for code that setups symbol tables, kernel based events, etc this is the wrong thing to do as that code is only called when a checkpoint isn't being restored from.
2012-03-09ARM: Fix valgrind reported error on O3 that was causing minor stats changes.Ali Saidi