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AgeCommit message (Expand)Author
2011-06-19inorder: stall stores on store conditionals & compare/swapsKorey Sewell
2011-06-19alpha: make hwrei a control instKorey Sewell
2011-06-19inorder: make InOrder CPU FS compilable/visibleKorey Sewell
2011-06-19inorder: remove memdep tracking for default pipelineKorey Sewell
2011-06-19inorder: fetchBuffer trackingKorey Sewell
2011-06-19inorder: redefine DynInst FP result typeKorey Sewell
2011-06-19inorder: treat SE mode syscalls as a trapping instructionKorey Sewell
2011-06-19inorder: bug in mduKorey Sewell
2011-06-19inorder: optionally track faulting instructionsKorey Sewell
2011-06-19inorder: cleanup events in resource poolKorey Sewell
2011-06-19inorder: don't stall after storesKorey Sewell
2011-06-19inorder: don't stall after storesKorey Sewell
2011-06-19inorder: remove decode squashKorey Sewell
2011-06-19inorder: support for compare and swap instsKorey Sewell
2011-06-19inorder: branch predictor updateKorey Sewell
2011-06-19inorder: priority for grad/squash eventsKorey Sewell
2011-06-19inorder: remove stalls on trap squashKorey Sewell
2011-06-19inorder: no dep. tracking for zero regKorey Sewell
2011-06-19imported patch recoverPCfromTrapKorey Sewell
2011-06-19imported patch squash_from_next_stageKorey Sewell
2011-06-19inorder: add flatDestReg member to dyninstKorey Sewell
2011-06-19inorder: update event prioritiesKorey Sewell
2011-06-19inorder: implement trap handlingKorey Sewell
2011-06-19inorder: cleanup intercomm. structs/squash infoKorey Sewell
2011-06-19inorder: use setupSquash for misspeculationKorey Sewell
2011-06-19sparc: init. cache state in TLBKorey Sewell
2011-06-19inorder: DynInst handling of stores for big-endian ISAsKorey Sewell
2011-06-19inorder: make marking of dest. regs an explicit requestKorey Sewell
2011-06-19inorder: simplify handling of split accessesKorey Sewell
2011-06-19inorder: addtl functionaly for inst. skedsKorey Sewell
2011-06-19inorder: register file statsKorey Sewell
2011-06-19inorder: scheduling for nonspec instsKorey Sewell
2011-06-19inorder: find register dependencies "lazily"Korey Sewell
2011-06-19inorder: assert on macro-opsKorey Sewell
2011-06-19inorder: handle faults at writeback stageKorey Sewell
2011-06-19inorder: ISA-zero reg handlingKorey Sewell
2011-06-19inorder: update support for branch delay slotsKorey Sewell
2011-06-19inorder: inst. iterator cleanupKorey Sewell
2011-06-19cpus/isa: add a != operator for pcstateKorey Sewell
2011-06-19inorder: update bpred codeKorey Sewell
2011-06-19inorder: add types for dependency checksKorey Sewell
2011-06-19inorder: use flattenIdx for reg indexingKorey Sewell
2011-06-19simple-thread: give a name() function for debugging w/the SimpleThread objectKorey Sewell
2011-06-19inorder: use m5_hash_map for skedCacheKorey Sewell
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-06-16ARM: Handle case where new TLB size is different from previous TLB size.Ali Saidi
2011-06-16ARM: Fix memset on TLB flush and initializationChander Sudanthi
2011-06-14Ruby: Correct set LONG_BITS and INDEX_SHIFT in class Set.Nilay Vaish
2011-06-12Loader: Handle bad section names when loading an ELF file.Gabe Black
2011-06-10o3: missing newlines on some dprintfsKorey Sewell
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