gem5 - gem5

Age	Commit message (Expand)	Author
2013-08-19	cpu: Fix TrafficGen trace playback	Sascha Bischoff
2013-08-19	mem: Use STL deque in favour of list for DRAM queues	Andreas Hansson
2013-08-19	mem: Perform write merging in the DRAM write queue	Andreas Hansson
2013-08-19	mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAM	Amin Farmahini
2013-08-19	cpu: Fix timing CPU drain check	Andreas Hansson
2013-08-19	alpha: Check interrupts before quiesce	Andreas Hansson
2013-08-19	stats: Fix issue when printing 2D vectors	Sascha Bischoff
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-08-19	mem: Warn instead of panic for tXAW violation	Andreas Hansson
2013-08-19	mem: Allow disabling of tXAW through a 0 activation limit	Andreas Hansson
2013-08-19	mem: Add an internal packet queue in SimpleMemory	Andreas Hansson
2013-08-19	cpu: Fix a bug in the O3 CPU introduced by the cache line patch	Andreas Hansson
2013-08-07	ruby: slicc: remove double trigger, continueProcessing	Nilay Vaish
2013-08-07	ruby: slicc: move some code to AbstractController	Nilay Vaish
2013-08-07	x86: add tlb checkpointing	Nilay Vaish
2013-07-19	cpu: Remove unused getBranchPred() method from BaseCPU	Andreas Sandberg
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-07-18	mem: Add cache class destructor to avoid memory leaks	Xiangyu Dong
2013-07-18	sim: Make MaxTick in Python match the one in C++	Andreas Hansson
2013-07-15	loader: Load weak symbols for function tracing	Deyuan Guo
2013-07-15	debug : Fixes the issue wherein Debug symbols were not getting dumped into tr...	Umesh Bhaskar
2013-07-11	dev: make BasicPioDevice take size in constructor	Steve Reinhardt
2013-07-11	dev: consistently end device classes in 'Device'	Steve Reinhardt
2013-07-11	dev/arm: get rid of AmbaDev namespace	Steve Reinhardt
2013-07-11	devices: make more classes derive from BasicPioDevice	Steve Reinhardt
2013-07-11	ruby: removed the very old double trigger hack	Brad Beckmann
2013-06-28	ruby: append transition comment only when in opt/debug	Nilay Vaish
2013-06-28	ruby: network: remove reconfiguration code	Nilay Vaish
2013-06-27	mem: Reorganize cache tags and make them a SimObject	Prakash Ramrakhyani
2013-06-27	mem: Remove the cache builder	Andreas Hansson
2013-06-27	config: Remove Clock parameter multiplication	Andreas Hansson
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Add a system clock command-line option	Akash Bagdia
2013-06-27	config: Remove redundant explicit setting of default clocks	Akash Bagdia
2013-06-27	mem: Tidy up the bridge with const and additional checks	Andreas Hansson
2013-06-27	mem: Fix CommMonitor style and response check	Andreas Hansson
2013-06-27	mem: Align cache timing to clock edges	Andreas Hansson
2013-06-27	cpu: Consider instructions waiting for FU completion in draining	Andreas Hansson
2013-06-27	mem: Cycles converted to Ticks in atomic cache accesses	Andreas Hansson
2013-06-27	base: Fix address range granularity calculation	Andreas Hansson
2013-06-27	mem: Remove a redundant heap allocation for a snoop packet	Andreas Hansson
2013-06-27	mem: Remove CoherentBus snoop port unused private member	Andreas Hansson
2013-06-27	stats: Remove printing of SparseHist total	Sascha Bischoff
2013-06-25	ruby: moesi cmp directory: separate actions for external hits	Nilay Vaish
2013-06-25	ruby: mesi cmp directory: separate actions for external hits	Nilay Vaish
2013-06-25	ruby: profiler: lots of inter-related changes	Nilay Vaish
2013-06-24	ruby: remove the three files related to profiling	Nilay Vaish
2013-06-24	ruby: MessageBuffer: Remove unused m_size variable	Joel Hestness ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-06-20	ruby: fix typo in MOESI_CMP_token protocol	Lena Olson
2013-06-18	ruby: Fix prefetching for MESI_CMP_Directory	Lena Olson