summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2007-01-03Add 'Time' as a parameter type that can accept variousNathan Binkert
formats for time (strings, datetime objects, etc.) Advance system time to 1/1/2009 Clean up time management code a little bit --HG-- extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
2006-12-30Fix up previous commit to proper logic.Kevin Lim
src/cpu/o3/commit_impl.hh: Oops, changed the logic a little bit. Fix it up to how it used to be. --HG-- extra : convert_revision : df7f69b0997207b611374c3c92880f3a405e88be
2006-12-29Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
into iceaxe.:/Volumes/work/m5/incoming --HG-- extra : convert_revision : dad5311afaaf40c1378017514c8b3f73852f13f5
2006-12-29FormattingNathan Binkert
--HG-- extra : convert_revision : f5a940a8b9aaba0703781b398cf29be581907c21
2006-12-27Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
2006-12-27Bug fixes in the TLBAli Saidi
Make our replacement algorithm same as legion (although not same as the spec) itb should be 64 entries not 48 src/arch/sparc/tlb.cc: Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) src/arch/sparc/tlb.hh: Make our replacement algorithm same as legion (although not same as the spec) src/python/m5/objects/SparcTLB.py: itb should be 64 entries too --HG-- extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
2006-12-27Compare legion and m5 tlbs for differencesAli Saidi
Only print faults instructions that aren't traps or faulting loads src/cpu/exetrace.cc: Compare the legion and m5 tlbs and printout any differences Only show differences if the instruction isn't a trap and isn't a memory operation that changes the trap level (a fault) src/cpu/m5legion_interface.h: update the m5<->legion interface to add tlb data --HG-- extra : convert_revision : 6963b64ca1012604e6b1d3c5e0e5f5282fd0164e
2006-12-27Change MemoryAccess dprintfs to print the data as wellAli Saidi
--HG-- extra : convert_revision : 51336fffa5e51a810ad2f6eb29b91c1bfd67824b
2006-12-27No need to use NULL, just use 0Nathan Binkert
The result of operator= cannot be an l-value --HG-- extra : convert_revision : df97a57f466e3498bd5a29638cb9912c7f3e1bd4
2006-12-26Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.Kevin Lim
--HG-- extra : convert_revision : 5c334ec806305451b3883c7fd0ed9cd695c038bc
2006-12-24Make sure that all of the bits in the result are setNathan Binkert
to some value. --HG-- extra : convert_revision : 1f1700fd77531cbb8cfad7f04ce2b573fcdefdab
2006-12-24remove some output formatting stuff that we don't useNathan Binkert
--HG-- extra : convert_revision : 367917499d3d7aebd0a91dad28c915bc85def624
2006-12-21Fix copyrightNathan Binkert
--HG-- extra : convert_revision : 8ad7824885a5c4da80175c47ba5288aab55b06ca
2006-12-21Expose the C++ event queue to python via the python functionNathan Binkert
m5.internal.event.create(). It takes a python object and a Tick and calls process() when the Tick occurs. --HG-- extra : convert_revision : 5e4c9728982b206163ff51e6850a1497d85ad7a3
2006-12-21styleNathan Binkert
--HG-- extra : convert_revision : 6bbaaa88a608081eebf706ff30293f38729415aa
2006-12-21Create a wrapper function to more easily add swig stuff to the buildNathan Binkert
--HG-- extra : convert_revision : 3aaf540a9e314a88a8945579398f0d79aa85d5cf
2006-12-21move the swig initialization calls from src/sim/main.cc toNathan Binkert
src/python/swig/init.cc so that it's not as easy to forget about it when you add a new swig module. --HG-- extra : convert_revision : 5cc4ec0838e636aa761901effb8986de58d23e03
2006-12-20don't use (*activeThreads).begin(), use activeThreads->blah().Nathan Binkert
Also don't call (*activeThreads).end() over and over. Just call activeThreads->end() once and save the result. Make sure we always check that there are elements in the list before we grab the first one. --HG-- extra : convert_revision : d769d8ed52da99532d57a9bbc93e92ddf22b7e58
2006-12-20Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
into iceaxe.:/Volumes/work/m5/incoming --HG-- extra : convert_revision : c1724538f27091e16ca495c8fdf2df06f55f7668
2006-12-20<scold> Make sure that variables are always initalized! </scold>Nathan Binkert
--HG-- extra : convert_revision : 1e946d9b1e1def36f9b8a73986dabf1b77096327
2006-12-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head --HG-- extra : convert_revision : 4bd4f8bb8e48e09562a2d9ae6eb7d061be973c5e
2006-12-19Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : fa8ce7149973245a73bb562b9378db13be647a14
2006-12-19fix twinx loads a little bitAli Saidi
bugfixes and demap implementation in tlb ignore some more differencs for one cycle src/arch/sparc/isa/formats/mem/blockmem.isa: twinx has 2 micro-ops src/arch/sparc/isa/formats/mem/util.isa: fix the fault check for twinx src/arch/sparc/tlb.cc: tlb bugfixes and write demapping code src/cpu/exetrace.cc: don't halt on a couple more instruction (ldx, stx) when things differ beacuse of the way tlb faults are handled in legion. --HG-- extra : convert_revision : 1e156dead6ebd58b257213625ed63c3793ef4b71
2006-12-18Streamline Cache/Tags interface: get rid of redundant functions,Steve Reinhardt
don't regenerate address from block in cache so that tags can turn around and use address to look up block again. --HG-- extra : convert_revision : 171018aa6e331d98399c4e5ef24e173c95eaca28
2006-12-18No need to template prefetcher on cache TagStore type.Steve Reinhardt
--HG-- rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc extra : convert_revision : 56c0b51e424a3a6590332dba4866e69a1ad19598
2006-12-18Get rid of generic CacheTags object (fold back into Cache).Steve Reinhardt
--HG-- extra : convert_revision : 8769bd8cc358ab3cbbdbbcd909b2e0f1515e09da
2006-12-18Fix unittest compilesNathan Binkert
--HG-- extra : convert_revision : 1163437081e1f1eab3f4512d04317dc94a673b9b
2006-12-18cast chars to int when we want to print integers so we get a numberNathan Binkert
instead of a character --HG-- extra : convert_revision : 7bfa88ba23ad057b751eb01a80416d9f72cfe81a
2006-12-18move the twinx loads to the correct opcode and add asis 0x24 and 0x27Ali Saidi
Make the TLB ok to translate QUAD_LDD src/arch/sparc/isa/decoder.isa: move the twinx loads to the correct opcode. src/arch/sparc/tlb.cc: Make QUAD_LDD asi ok to execute --HG-- extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
2006-12-17Compilation fixes.Gabe Black
--HG-- extra : convert_revision : 4932ab507580e0c9f7012398e71921ce58fc3c4e
2006-12-17Added in the extended twin load formatGabe Black
src/arch/sparc/isa/decoder.isa: Added the extended twin load instructions src/arch/sparc/isa/formats/mem/blockmem.isa: Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later. --HG-- extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
2006-12-16Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/sparcfs --HG-- extra : convert_revision : c8718b3df72b8c951c24742e8ce517a93bc23fe9
2006-12-16Merge zizzer:/bk/sparcfs/Gabe Black
into zower.eecs.umich.edu:/eecshome/m5/sparcfs --HG-- extra : convert_revision : 2764b356ef01d1fcb6ed272e4ef96179cd651d4e
2006-12-16Support for twin loads.Gabe Black
src/arch/sparc/isa/decoder.isa: Changed the names of the twin loads to match the 2005 spec. They still use the old format though. src/arch/sparc/isa/formats/mem/blockmem.isa: Added code to generate twin loads src/arch/sparc/isa/formats/mem/util.isa: Added an alignment check for twin loads src/arch/sparc/isa/operands.isa: Comment explaining twin load operands. --HG-- extra : convert_revision : ad42821a97dcda17744875b1e5dc00a9642e59b7
2006-12-16Compiler error fix.Gabe Black
--HG-- extra : convert_revision : 39e2638a10bf3e821e8f3d4d8c664008c98fc921
2006-12-15Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : a6a40a3bc2e07bc7828de08fa2ce1c847105483d
2006-12-15small change to eliminate address range overlap.Lisa Hsu
--HG-- extra : convert_revision : c8309a8774265a707c87c4f516bec1f81aff4a79
2006-12-15little fixes i noticed while searching for reason for address range issues ↵Lisa Hsu
(but these weren't the cause of the problem). RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you. src/cpu/memtest/memtest.hh: src/cpu/o3/fetch.hh: src/cpu/o3/lsq.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/simple/atomic.hh: src/cpu/simple/timing.hh: Fix RangeSize arguments src/dev/alpha/tsunami_cchip.cc: src/dev/alpha/tsunami_io.cc: src/dev/alpha/tsunami_pchip.cc: src/dev/baddev.cc: pioSize indicates SIZE, not a mask --HG-- extra : convert_revision : d385521fcfe58f8dffc8622260937e668a47a948
2006-12-15Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d
2006-12-15some small general fixes to make everythign work nicely with other ISAs, now ↵Lisa Hsu
we can merge back with newmem. exetrace.cc: wrap this variable between FULL_SYSTEM #ifs mmaped_ipr.hh: fix for build miscregfile.cc: fixes for HPSTATE access during SE mode src/arch/sparc/miscregfile.cc: fixes for HPSTATE access during SE mode src/arch/mips/mmaped_ipr.hh: fix for build src/cpu/exetrace.cc: wrap this variable between FULL_SYSTEM #ifs --HG-- extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
2006-12-15tlb.cc:Lisa Hsu
fix namespace indentations src/arch/alpha/tlb.cc: fix namespace indentations --HG-- extra : convert_revision : 327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
2006-12-15Use my range_map to speed up findPort() in the bus. The snoop code could ↵Ali Saidi
still use some work. --HG-- extra : convert_revision : ba0a68bd378d68e4ebd80a101b965d36c8be1db9
2006-12-15Optimized the TLB translations with some cachingAli Saidi
--HG-- extra : convert_revision : f79f863393f918ff9363b2c261f8c0dfec64312e
2006-12-14flesh out twinx asisAli Saidi
fix TICK register reads reduce the number of readmiscreg accesses, implement tsb pointer stuff src/arch/sparc/asi.cc: flesh out twinx asis src/arch/sparc/miscregfile.cc: fix TICK register reads src/arch/sparc/tlb.cc: reduce the number of readmiscreg accesses, implement tsb pointer stuff --HG-- extra : convert_revision : 1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
2006-12-13Split CachePort class into CpuSidePort and MemSidePortSteve Reinhardt
and push those into derived Cache template class to eliminate a few layers of virtual functions and conditionals ("if (isCpuSide) { ... }" etc.). --HG-- extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
2006-12-13Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 8cf3e824e4892249b12ed0fd92bb310748b18fa2
2006-12-13fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.Lisa Hsu
--HG-- extra : convert_revision : 4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
2006-12-13Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
2006-12-13Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : c6d174716641f0b8286b8478bcb9053b3eec54e3
2006-12-12Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-13 12:40:18 +0000