summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2015-08-04mem: Add probe support to the CommMonitorAndreas Sandberg
2015-08-03sim: function for testing for auto deletionTimothy Jones
2015-08-03uby: Fix checkpointing and restoreTimothy Jones
2015-08-03ruby: mesi three level: multiple corrections to the protocolNilay Vaish
2015-08-03ruby: mesi two,three level: copy data only when dirtyNilay Vaish
2015-08-01ruby: removed invalid assert in message comparitorBrad Beckmann
2015-07-20ruby: improved stall and wait debuggingBrad Beckmann
2015-07-20slicc: fix error in conflicing symbol declarationBrad Beckmann
2015-07-20slicc: enable overloading in functions not in classesBrad Beckmann
2015-07-20ruby: change router pipeline stages to 2David Hashe
2015-07-20ruby: change advance_stage for flit_dDavid Hashe
2015-07-20slicc: improved stalling support in protocolsBrad Beckmann
2015-07-20ruby: expose access permission to replacement policiesDavid Hashe
2015-07-20ruby: adds size and empty apis to the msg buffer stallmapDavid Hashe
2015-07-20ruby: fix deadlock bug in banked array resource checksDavid Hashe
2015-07-20ruby: Fix for stallAndWait bugDavid Hashe
2015-07-20mem: add request types for acquire and releaseDavid Hashe
2015-07-20ruby: allocate a block in CacheMemory without updating LRU stateDavid Hashe
2015-07-20ruby: speed up function used for cache walksDavid Hashe
2015-07-20slicc: support for arbitrary DPRINTF flags (not just RubySlicc)David Hashe
2015-07-20slicc: support for local variable declarations in action blocksDavid Hashe
2015-07-20ruby: initialize replacement policies with their own simobjsDavid Hashe
2015-07-20ruby: give access to cache tag/data latencies from SLICCDavid Hashe
2015-07-20slicc: support for multiple cache entry types in the same state machineDavid Hashe
2015-07-20slicc: Fix bug in enqueue and peek statements.David Hashe
2015-07-20slicc: fix missing inline function in LocalVariableASTDavid Hashe
2015-07-20slicc: improve support for prefix operationsDavid Hashe
2015-07-20slicc: support for transitions with a wildcard next stateDavid Hashe
2015-07-20slicc: support for multiple message types on the same bufferDavid Hashe
2015-08-01slicc: fatal->panic on invalid transitionsBrad Beckmann
2015-07-20mem: Hit callback delay fixDavid Hashe
2015-07-20cpu: Fixed a bug on where to fetch the next instruction fromDavid Hashe
2015-07-20x86: x86 instruction-implementation bug fixesDavid Hashe
2015-07-20ruby: re-added the addressToInt slicc interface functionBrad Beckmann
2015-07-20syscall: Add readlink to x86 with special case /proc/self/exeDavid Hashe
2015-07-20ruby: add useful dprints to sequencerBrad Beckmann
2015-07-20slicc: isinstance bugfixDavid Hashe
2015-07-31cpu: Update debug message from Fetch1 isDrained() in MinorAndreas Sandberg
2015-07-31cpu: Fix Minor drain issues when switched outAndreas Sandberg
2015-07-30cpu: Only activate thread 0 in Minor if the CPU is activeAndreas Sandberg
2015-07-30cpu: Fix drain issues in the Minor CPUAndreas Sandberg
2015-07-30mem: Add missing clean eviction on uncacheable accessAndreas Hansson
2015-07-30mem: Remove unused RequestCause in cacheAndreas Hansson
2015-07-30mem: Make caches way awareDavid Guillen-Fandos
2015-07-30mem: Transition away from isSupplyExclusive for writebacksAndreas Hansson
2015-07-30mem: Tidy up CacheBlk classAndreas Hansson
2015-07-30mem: Tidy up packetAndreas Hansson
2015-07-30cpu: Fix issue identified by UBSanAndreas Hansson
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 02:47:50 +0000