Age | Commit message (Collapse) | Author |
|
src/arch/sparc/floatregfile.cc:
fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
fix printing of float registers
--HG--
extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
|
|
src/SConscript:
strip doesn't take a src and dest in solaris
--HG--
extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
|
|
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : 276b640c5c5a51e88e9bd630960ad462d9f0cb8d
|
|
--HG--
extra : convert_revision : 2cc0d0144abab264aa0ec8c07242cdab2dffd4f8
|
|
src/arch/sparc/floatregfile.cc:
Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
fix serialization for intreg
src/arch/sparc/miscregfile.cc:
fix serialization from miscreg
src/arch/sparc/pagetable.cc:
fix serialization for page table
src/arch/sparc/regfile.cc:
need to serialize nnpc
src/arch/sparc/tlb.cc:
write serialization code for tlb
src/cpu/base.cc:
provide a way to find the thread number a context is
serialize the instruction counter
src/cpu/base.hh:
provide a way to find the thread number a context is
and given a thread number find a context pointer
src/cpu/cpuevent.hh:
provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
Make findObj() work (it hasn't since we did the python conversion stuff)
--HG--
extra : convert_revision : a95bc4e3c3354304171efbe3797556fdb146bea2
|
|
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 7b332ee4c737206511d26db391117eb1fe5ea290
|
|
src/arch/sparc/isa/base.isa:
Added passesFpCondition function to help with fbfcc and fbpfcc instructions.
src/arch/sparc/isa/decoder.isa:
Added fbfcc and fbpfcc instructions, and cleaned up branch code slightly.
src/arch/sparc/isa/formats/branch.isa:
Minor cleanup.
--HG--
extra : convert_revision : 6586b46418f1f70bace41407f267fee30c657714
|
|
way to do this.
--HG--
extra : convert_revision : 4f59ca8e6425db23f57a1f3f65a4874e483d0ecc
|
|
--HG--
extra : convert_revision : 06be0f8572e26c3c7e761b482248304ce1afa038
|
|
of the pointer, not the memory.
--HG--
extra : convert_revision : 04647d9fa0c464960d37797717f8171862cf48f8
|
|
setSingleStep
--HG--
extra : convert_revision : fde27a1faa6c03a24a4321a153dfa89a438f9a32
|
|
--HG--
extra : convert_revision : 84717cd3a8fa9fb85bd0693304e05ef475b05d07
|
|
unimplemented floating point ops.
--HG--
extra : convert_revision : 356fec86c35560b20ea8eee80844602bbcec145f
|
|
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 0e4a54c21f32fec13deaf00b5d61c258007f172b
|
|
--HG--
extra : convert_revision : 36137ee025dc5c79665b041b43bd89505715ca70
|
|
right with respect to quite NaNs, but hopefully we don't need to worry about the distinction.
--HG--
extra : convert_revision : 67b6583a20530b7a393aa04d0b71031d3c72ecdd
|
|
--HG--
extra : convert_revision : d2c538e7f469bd12a80eb8585c78d5325d6e6141
|
|
--HG--
extra : convert_revision : f2b80a0b7768edc370e3f07c45cb3bb9a46450a9
|
|
--HG--
extra : convert_revision : 4e83e5163076aeef72ec5caf1e0d7adea11da875
|
|
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : 7b8b791815d1fb51cc7ad085307a640b2ee51642
|
|
--HG--
extra : convert_revision : 4665ac7760c9b78a1d7699ceeb541b694211a947
|
|
--HG--
extra : convert_revision : 1eaabd13c72aa42c512a04d162a87491818bc621
|
|
--HG--
extra : convert_revision : f9c78e86b60c3085cd95b1b4e132205e0ef584dd
|
|
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 7bea2cb13e2de527134d98d4ee21a55dc4a7d1ad
|
|
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : e302dc4d7a20646bb0ea363127b2658a6d6e810c
|
|
into pb15.local:/Users/ali/work/m5.newmem.head
--HG--
extra : convert_revision : b4db0b350c8a5b3452ede74e5b42eec8ed6685c3
|
|
return correct traps for ua2005 fpops that aren't implemented in hw
--HG--
extra : convert_revision : 998fd43f77c5de7078bac1c6caab296b18c9366d
|
|
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : f25fd4855a1eaaecb29e6ccc3cee22cf07e4108b
|
|
make fp writes also chatty with the Sparc traceflag
src/arch/sparc/floatregfile.cc:
make fp writes also chatty with the Sparc traceflag
src/cpu/exetrace.cc:
fix comparing fp registers between legion and m5
--HG--
extra : convert_revision : f3703afae56249f137451262bc1b6919d465e714
|
|
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 2398e48722dd71ddf270e93bd7b387078fb30e6b
|
|
the other param code so that other functions can use it
as well.
--HG--
extra : convert_revision : a8becdeadc70af0b64bff5b0770788dfba6e1857
|
|
--HG--
extra : convert_revision : 2fa44718e381ff743fa1cf12f4db2221dca87e4c
|
|
SConstruct:
src/SConscript:
Add flags for Intel CC while i'm at it
src/base/compiler.hh:
the _Pragma stuff needst to be called this way unless someone happens to have a cleaner way
src/base/cprintf_formats.hh:
add std:: where appropriate
src/base/statistics.hh:
use this->map since icc was getting confused about std::map vs the locally defined map
src/cpu/static_inst.hh:
Add some more dummy returns where needed
src/mem/packet.hh:
add more dummy returns where needed
src/sim/host.hh:
use limits to come up with max tick
--HG--
extra : convert_revision : 08e9f7898b29fb9d063136529afb9b6abceab60c
|
|
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge
--HG--
extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c
|
|
--HG--
extra : convert_revision : a79f5ee225208338594e7c4ecf0a71fef941918c
|
|
possible now becauase Ctrl_Base_DepTag gets added into control register numbers.
--HG--
extra : convert_revision : d6de3be277127547cd942769cd34a54a4ec8db32
|
|
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : ca6e616e64d4528478c1505dc7ce111b8888d389
|
|
--HG--
extra : convert_revision : 4b570a33a951e9286b38873b2be3651ffaee8532
|
|
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : 53ee81b099930d4d827db99e2d944ffb8645c706
|
|
some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct
src/arch/sparc/floatregfile.cc:
Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
some fixes to fp instructions to use the single precision registers
fix smul again
fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
if this is an fp op emit fp check code
src/cpu/exetrace.cc:
check fp regs as well as int regs
src/cpu/m5legion_interface.h:
add fpregs to m5legion struct
--HG--
extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232
|
|
into zeep.pool:/z/saidi/work/m5.suncc
--HG--
extra : convert_revision : 1706f6218abec7eb575dcff3ad4aef83894f64ab
|
|
into zeep.pool:/z/saidi/work/m5.suncc
--HG--
extra : convert_revision : 20f61a524a3b53fc0afcf53a24b5a1fe1d96f579
|
|
pretty close to compiling w/ suns compiler
briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops
SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
--HG--
extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
|
|
not just MaxGL.
--HG--
extra : convert_revision : 6fd090f112611db1e72a1f129dff03687d52930a
|
|
into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
--HG--
extra : convert_revision : 1b854ec7caa33d3009383754206b643494c4c42d
|
|
--HG--
extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
|
|
--HG--
extra : convert_revision : 9398362237443dc659f423a342bd27c923e90aea
|
|
into zeep.pool:/y/binkertn/research/m5/rtc
--HG--
extra : convert_revision : 65ddda89f38c5fa874722c20e5d82ed1bb4e12d9
|
|
pass the tuple of python's struct_time and interpret that.
Fixes a problem where the local timezone leaked into the time
calculation. Also fix things so that the unix, python, and RTC
data sheets all get the right time. Provide both years since 1900
and BCD two digit year.
Put the date back at 1/1/2006 for now.
--HG--
extra : convert_revision : 473244572f468de2cb579a3dd7ae296a6f81f5d7
|
|
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
src/arch/sparc/isa/decoder.isa:
fix smul and sdiv to sign extend, and handle overflow/underflow corretly
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/formats/mem/blockmem.isa:
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/includes.isa:
Use limits for 32bit underflow/overflow detection
src/arch/sparc/tlb.cc:
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
src/arch/sparc/tlb_map.hh:
add a print function to dump the tlb lookup table
src/cpu/simple/base.cc:
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
--HG--
extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4
|