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AgeCommit message (Expand)Author
2008-12-08eventq: Add some debugging code to the eventq.Nathan Binkert
2008-12-08output: Change default output directory and files and update tests.Nathan Binkert
2008-12-07Devices: Clean up the IDE controller.Gabe Black
2008-12-07imported patch aux-fix.patchLisa Hsu
2008-12-06X86: Add add_entry back in.Gabe Black
2008-12-06eventq: use the flags data structureNathan Binkert
2008-12-06eventq: move virtual function definitiions to the .cc file.Nathan Binkert
2008-12-06traceflags: Make "All" a valid trace flag.Nathan Binkert
2008-12-06SimObject: change naming of vectors so there are the same numbers of digits.Nathan Binkert
2008-12-06flags: Change naming of functions to be clearerNathan Binkert
2008-12-05IGbE: Add support for newer 8257x based Intel NICsAli Saidi
2008-12-05IGbE: Add support for TCP segment offloadAli Saidi
2008-12-05INet: Allow updating on id, len, seq, and flag field for TCP segment offloadAli Saidi
2008-12-05Automated merge with ssh://m5sim.org//repo/m5Lisa Hsu
2008-12-05This brings M5 closer to modernity - the kernel being advertised is newer so ...Lisa Hsu
2008-12-04This patch pulls out the auxiliary vector struct from individual ISALisa Hsu
2008-12-03cprintf: support a configurable width and precision ("*" in printf)Nathan Binkert
2008-11-20Assume files w/o obvious OS are Linux (with warning)Steve Reinhardt
2008-11-17Sort trace flags before printing them.Steve Reinhardt
2008-11-15Output: Include gzstream package to allow automatically-gzipped outputClint Smullen
2008-11-15syscalls: fix latent brk/obreak bug.Steve Reinhardt
2008-11-14Cache: get rid of obsolete Tag methods.Steve Reinhardt
2008-11-14Fix a bunch of bugs I introduced when I changed the flags stuff for packets.Nathan Binkert
2008-11-13CPU: Refactor read/write in the simple timing CPU.Gabe Black
2008-11-10SCons: Allow top level directory of EXTRAS able to contain SConscripts.Nathan Binkert
2008-11-10pseudo inst: Add rpns (read processor nanoseconds) instruction.Nathan Binkert
2008-11-10Clean up the SimpleTimingPort class a little bit.Nathan Binkert
2008-11-10clean: Move some stuff from the hh file to the cc file.Nathan Binkert
2008-11-10python: Fix the reference counting for python events placed on the eventq.Nathan Binkert
2008-11-10O3CPU: Make the instcount debugging stuff per-cpu.Clint Smullen
2008-11-10mem: update stuff for changes to Packet and RequestNathan Binkert
2008-11-10style: clean up the Packet stuffNathan Binkert
2008-11-10flags: Provide an object for managing boolean flags for an object.Nathan Binkert
2008-11-10safe_cast: add a new cast function for casts that should always succeed.Nathan Binkert
2008-11-10DmaDevice: fix minor type in error message.Steve Reinhardt
2008-11-10mem: Assert that requests have non-negative size.Steve Reinhardt
2008-11-10Cache: Refactor packet forwarding a bit.Steve Reinhardt
2008-11-09CPU: Make unaligned accesses work in the timing simple CPU.Gabe Black
2008-11-09X86: Fix completeAcc get call.Gabe Black
2008-11-09X86: Make the timing simple CPU handle variable length instructions.Gabe Black
2008-11-05Fix a few more places where the context stuff wasn't changedNathan Binkert
2008-11-05Fix SPARC_FS compileLisa Hsu
2008-11-05Right now a single thread cpu 1 could get assigned context Id != 1, dependingLisa Hsu
2008-11-04decouple eviction from insertion in the cache.Lisa Hsu
2008-11-04Change the findBlock(addr, lat) to accessBlock, which I think has better conn...Lisa Hsu
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02Make it so that all thread contexts are registered with the System, even inLisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-10-27CPU: The API change to EventWrapper did not get propagated to the entirety o...Clint Smullen