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2011-03-02X86: Use the npc as the pc when doing a nativetrace, not what M5 considers ↵Gabe Black
the pc.
2011-03-02X86: Decode the mysterious and elusive ffreep x87 instruction.Gabe Black
The internet says this instruction was created by accident when an Intel CPU failed to decode x87 instructions properly. It's been documented on a few rare occasions and has generally worked to ensure backwards compatability. One source claims that the gcc toolchain is basically the only thing that emits it, and that emulators/binary translators like qemu and bochs implement it. We won't actually implement it here since we're hardly implementing any other x87 instructions either. If we were to implement it, it would behave the same as ffree but then also pop the register stack. http://www.pagetable.com/?p=16
2011-03-01Spelling: Fix the a spelling error by changing mmaped to mmapped.Gabe Black
There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped. --HG-- rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
2011-03-01X86: Mark IO reads and writes as non-speculative.Gabe Black
2011-03-01X86: Mark prefetches as such in their instruction and request flags.Gabe Black
2011-03-01Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBufferNilay Vaish
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF() has not been provided with correct number of arguments. The patch fixes these bugs.
2011-03-01Ruby: Mention that Ruby's bound checking option only applies to Ruby.Gabe Black
2011-02-27X86: If PCI config space is disabled, pass through to regular IO addresses.Gabe Black
2011-02-27X86: Use regular read requests in the walker instead of read exclusive.Gabe Black
2011-02-26getopt: Remove GPL code.Nathan Binkert
This code is unused and should never have been committed
2011-02-25Ruby: Remove store bufferNilay Vaish
This patch removes the store buffer from Ruby. It is not in use currently. Since libruby is being and store buffer makes calls to libruby, it is not possible to maintain it until substantial changes are made.
2011-02-25Ruby: Remove librubyNilay Vaish
This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It moves the contents to libruby.hh to RubyRequest.hh and RubyRequest.cc files.
2011-02-25Ruby: Make Address.hh independent of RubySystemNilay Vaish
This patch changes Address.hh so that it is not dependent on RubySystem. This dependence seems unecessary. All those functions that depend on RubySystem have been moved to Address.cc file.
2011-02-25Ruby: Make DataBlock.hh independent of RubySystemNilay Vaish
This patch changes DataBlock.hh so that it is not dependent on RubySystem. This dependence seems unecessary. All those functions that depende on RubySystem have been moved to DataBlock.cc file.
2011-02-25O3CPU: Fix iqCount and lsqCount SMT fetch policies.Timothy M. Jones
Fixes two of the SMT fetch policies in O3CPU that were returning the count of instructions in the IQ or LSQ rather than the thread ID to fetch from.
2011-02-23ruby: automate permission settingBrad Beckmann
This patch integrates permissions with cache and memory states, and then automates the setting of permissions within the generated code. No longer does one need to manually set the permissions within the setState funciton. This patch will faciliate easier functional access support by always correctly setting permissions for both cache and memory states. --HG-- rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
2011-02-23MOESI_hammer: cache probe address clean upBrad Beckmann
2011-02-23ruby: cleaned up access permission enumBrad Beckmann
2011-02-23ruby: removed unsupported protocol filesBrad Beckmann
2011-02-23inorder: InstSeqNum bugKorey Sewell
Because int and not InstSeqNum was used in a couple of places, you can overflow the int type and thus get wierd bugs when the sequence number is negative (or some wierd value)
2011-02-23inorder: dyn inst initializationKorey Sewell
remove constructors that werent being used (it just gets confusing) use initialization list for all the variables instead of relying on initVars() function
2011-02-23inorder: cache packet handlingKorey Sewell
-use a pointer to CacheReqPacket instead of PacketPtr so correct destructors get called on packet deletion - make sure to delete the packet if the cache blocks the sendTiming request or for some reason we dont use the packet - dont overwrite memory requests since in the worst case an instruction will be replaying a request so no need to keep allocating a new request - we dont use retryPkt so delete it - fetch code was split out already, so just assert that this is a memory reference inst. and that the staticInst is available
2011-02-23Mem: Print out memory when access > 8 bytesAli Saidi
2011-02-23ARM: Set ITSTATE correctly after FlushPipeAli Saidi
2011-02-23ARM: This panic can be hit during misspeculation so it can't exist.Ali Saidi
2011-02-23ARM: Bad interworking warn way to noisy when running real code w/misspeculation.Ali Saidi
2011-02-23O3: When a prefetch causes a fault, don't record it in the instAli Saidi
2011-02-23ARM: NEON instruction templates modified to set the predicate flag to false ↵Giacomo Gabrielli
when needed.
2011-02-23O3: If there is an outstanding table walk don't let the inst queue sleep.Ali Saidi
If there is an outstanding table walk and no other activity in the CPU it can go to sleep and never wake up. This change makes the instruction queue always active if the CPU is waiting for a store to translate. If Gabe changes the way this code works then the below should be removed as indicated by the todo.
2011-02-23ARM: Squash state on FPSCR stride or len write.Ali Saidi
2011-02-23ARM: Mark store conditionals as such.Matt Horsnell
2011-02-23ARM: Do something for ISB, DSB, DMBAli Saidi
2011-02-23ARM: Fix bug that let two table walks occur in parallel.Ali Saidi
2011-02-23Includes: Don't include isa_traits.hh and use the TheISA namespace unless ↵Ali Saidi
really needed.
2011-02-23ARM: Make Noop actually decode to a noop and set it's instflags.Ali Saidi
2011-02-23O3: Fix bug when a squash occurs right before TLB miss returns.Ali Saidi
In this case we need to throw away the TLB miss, not assume it was the one we were waiting for.
2011-02-23ARM: Delete OABI syscall handling.Ali Saidi
We only support EABI binaries, so there is no reason to support OABI syscalls. The loader detects OABI calls and fatal() so there is no reason to even check here.
2011-02-23CLCD: Fix some serialization bugs with the clcd controller.Ali Saidi
2011-02-23ARM: Add support for read of 100MHz clock in system controller.Ali Saidi
2011-02-23ARM: Reset simulation statistics when pref counters are reset.Ali Saidi
The ARM performance counters are not currently supported by the model. This patch interprets a 'reset performance counters' command to mean 'reset the simulator statistics' instead.
2011-02-23ARM: Adds dummy support for a L2 latency miscreg.Ali Saidi
2011-02-23ruby: extend dprintfs for RubyGenerated TraceFlagKorey Sewell
"executing" isnt a very descriptive debug message and in going through the output you get multiple messages that say "executing" but nothing to help you parse through the code/execution. So instead, at least print out the name of the action that is taking place in these functions.
2011-02-23ruby: cleaning up RubyQueue and RubyNetwork dprintfsKorey Sewell
Overall, continue to progress Ruby debug messages to more of the normal M5 debug message style - add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output isn't littered w/"global:" everywhere. - clean up messages that print over multiple lines when possible - clean up duplicate prints in the message buffer
2011-02-22m5: merged in hammer fixBrad Beckmann
2011-02-19Ruby: Machine Type missing in MOESI CMP directory protocolNilay Vaish
In certain actions of the L1 cache controller, while creating an outgoing message, the machine type was not being set. This results in a segmentation fault when trace is collected. Joseph Pusudesris provided his patch for fixing this issue.
2011-02-19Ruby: clean MOESI CMP directory protocolNilay Vaish
The L1 cache controller file contains references to foo and goo queues, which are not in use at all. These have been removed.
2011-02-18m5: merge inorder/release-notes/make_release changesKorey Sewell
2011-02-18inorder: add names and slot #s to res. dprintsKorey Sewell
2011-02-18inorder: ignore nops in execution unitKorey Sewell
2011-02-18inorder: update graduation unitKorey Sewell
make sure instructions are able to commit before writing back to the RF do not commit more than 1 non-speculative instruction per cycle
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