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AgeCommit message (Expand)Author
2018-11-27sim-se: only implement getdentsFunc on supported hostsCiro Santilli
2018-11-27systemc: set endianess to fix build for ARM hostCiro Santilli
2018-11-27base: Add some functions to convert floats to bits and vice versa.Gabe Black
2018-11-26mem-cache: Add setters to validate and secure blockDaniel R. Carvalho
2018-11-22cpu: Made LTAGE parameters configurablePau Cabre
2018-11-22cpu: Fixed useful counter handling in LTAGEPau Cabre
2018-11-22cpu: Fixes on the loop predictor part of LTAGEPau Cabre
2018-11-21x86: Get rid of a problematic DPRINTF in PremFp.Gabe Black
2018-11-20sim: Deschedule existing events when destructing an event queue.Gabe Black
2018-11-19base: Don't let exceptions leak from the to_number utility function.Gabe Black
2018-11-19systemc: Stop explicitly adding the systemc ext dir to CPPPATH.Gabe Black
2018-11-19systemc: Put systemc headers in the include path when supported.Gabe Black
2018-11-19systemc: Increase the stack size for the sc_main fiber to 8MB.Gabe Black
2018-11-18base: Set up a guard page for fiber stacks.Gabe Black
2018-11-18mem-cache: a missing cast was truncating addressesJavier Bueno
2018-11-17cpu: Fix LTAGE max number of allocations on updatePau Cabre
2018-11-17configs: Added an option for choosing branch predictor typePau Cabre
2018-11-16sim: Fix data type of ticks per second before passing it to C++Srikant Bharadwaj
2018-11-16mem: avoid calling regStat twice on a QoSPolicyMatteo Andreozzi
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
2018-11-15mem-cache: fix invalid iterator accessJavier Bueno
2018-11-15mem-cache: Make StridePrefetcher use Replacement PoliciesDaniel
2018-11-15mem-cache: Add invalidation function to StrideEntryDaniel
2018-11-15mem-cache: Make PCTable context independentDaniel
2018-11-15mem-cache: Vectorize StridePrefetcher's entries.Daniel
2018-11-15mem-cache: Return entry in StridePrefetcher::pcTableHit()Daniel
2018-11-15mem-cache: Cleanup prefetchersDaniel
2018-11-14cpu: Fixed ratio of pred to hyst bits for LTAGE BimodalPau Cabre
2018-11-14mem-cache: Remove Cache dependency from TagsDaniel R. Carvalho
2018-11-14mem-cache: Move access latency calculation to CacheDaniel R. Carvalho
2018-11-14arch-arm: Print register name when warning on AT instructionsGiacomo Travaglini
2018-11-14mem-cache: implement a probe-based interfaceJavier Bueno
2018-11-14sim: Move BitUnion overloading to show/parseParamsGiacomo Travaglini
2018-11-14sim: Move paramIn/Out definition to header fileGiacomo Travaglini
2018-11-13cpu: Fixed PC shifting on LTAGE branch predictorPau Cabre
2018-11-13mem-cache: Align how we handle requests in atomic with timingNikos Nikoleris
2018-11-12systemc: Push python headers on top of sourcesGiacomo Travaglini
2018-11-12systemc: Stop using python to set/manage the global time resolution.Gabe Black
2018-11-12sim: Push the global frequency management code into C++.Gabe Black
2018-11-09systemc: Get rid of a duplicated base class initializer for sc_fifo.Gabe Black
2018-11-09systemc: Add a missing "const" on one of the sc_event operators.Gabe Black
2018-11-09systemc: Only build python utility code if python is enabled.Gabe Black
2018-11-09systemc: Separate and conditionalize exposing sc_main to python.Gabe Black
2018-11-09systemc: Seperate out the sc_main fiber and its bookkeeping.Gabe Black
2018-11-09systemc: Stop using python init to set up predefined message ids.Gabe Black
2018-11-09systemc: Wrap some report maps in functions.Gabe Black
2018-11-07mem-ruby: Use Packet writing functions instead of memcpyDaniel R. Carvalho
2018-11-07arch-arm: Deprecate usage of legacy bootloader patchingGiacomo Travaglini
2018-11-07arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32Giacomo Travaglini
2018-11-07arch-arm: Implement AArch32 RVBARGiacomo Travaglini
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