gem5 - gem5

Age	Commit message (Expand)	Author
2010-11-20	random: small comment about our random number generator and its origin	Nathan Binkert
2010-11-19	SE: Fix simulating more than 4GB of RAM in SE mode	Ali Saidi
2010-11-19	SCons: Support building without an ISA	Ali Saidi
2010-11-18	O3: Fix fp destination register flattening, and index offset adjusting.	Gabe Black
2010-11-15	O3: Make O3 support variably lengthed instructions.	Gabe Black
2010-11-15	O3: reset architetural state by calling clear()	Ali Saidi
2010-11-15	ARM: Add comment about the organization of the IT state register	Ali Saidi
2010-11-15	CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.	Giacomo Gabrielli
2010-11-15	O3: prevent a squash when completeAcc() modifies misc reg through TC.	Min Kyu Jeong
2010-11-15	ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...	Ali Saidi
2010-11-15	SCons: Cleanup SCons output during compile	Ali Saidi
2010-11-15	ARM: Add a Keyboard Mouse Interface controller	William Wang
2010-11-15	ARM: Implement a CLCD Frame buffer	William Wang
2010-11-15	ARM: Add support for GDB on ARM	William Wang
2010-11-15	ARM: Make utility.hh meet style guidelines	Ali Saidi
2010-11-15	ARM: Add support for a dumb IDE controller	Ali Saidi
2010-11-15	ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.	Ali Saidi
2010-11-15	ARM: Add support for switching CPUs	Ali Saidi
2010-11-15	ARM: Use the correct delete operator for RFE	Ali Saidi
2010-11-15	ARM: Fix SRS instruction to micro-code memory operation and register update.	Ali Saidi
2010-11-15	CPU: Fix bug when a split transaction is issued to a faster cache	Ali Saidi
2010-11-15	ARM: Do something predictable for an UNPREDICTABLE branch.	Ali Saidi
2010-11-11	Params: Fix an off by one error and a misleading comment.	Gabe Black
2010-11-11	SimObject: Add a comment near clear_child that it's unlikely to be called.	Gabe Black
2010-11-11	SPARC: Clean up some historical style issues.	Gabe Black
2010-11-09	SimObject: Use "self" when calling the clear_child method.	Gabe Black
2010-11-08	X86: Fix X86_FS compilation.	Gabe Black
2010-11-08	ARM: Add some TLB statistics for ARM	Ali Saidi
2010-11-08	ARM: Add checkpointing support	Ali Saidi
2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi
2010-11-08	ARM: Keep the warnings to a minimum.	Ali Saidi
2010-11-08	Mem: Finish half-baked support for mmaping file in physmem.	Ali Saidi
2010-11-08	Bus: Have the I/O devices that return address ranges print them out.	Ali Saidi
2010-11-08	ARM: Don't return the result of a table walk the same cycle it's completed.	Ali Saidi
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2010-11-08	ARM: Make all ARM uops delayed commit.	Ali Saidi
2010-11-08	sim: Use forward declarations for ports.	Ali Saidi
2010-11-06	scons: Replace the build_dir parameter to SConscript with variant_dir.	Gabe Black
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-10-29	X86: Fault on divide by zero instead of panicing.	Gabe Black
2010-10-29	X86: Make syscalls also serialize after.	Gabe Black
2010-10-24	O3: Get rid of a bunch of commented out lines.	Gabe Black
2010-10-22	X86: Make nop a regular, non-microcoded instruction.	Gabe Black
2010-10-22	X86: Implement genMachineCheckFault.	Gabe Black
2010-10-22	X86: Make syscall instructions non-speculative in SE.	Gabe Black
2010-10-22	ISA: Simplify various implementations of completeAcc.	Gabe Black
2010-10-22	ARM: Don't pretend to writeback registers in initiateAcc.	Gabe Black
2010-10-18	cache: minor SC assertion fix	Steve Reinhardt
2010-10-17	MIPS: Get rid of the backdoor device copy/pasted from and only used in Alpha.	Gabe Black
2010-10-16	Mem: Reclaim some request flags used by MIPS for alignment checking.	Gabe Black