Age | Commit message (Collapse) | Author |
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are not processed as code.
src/arch/isa_parser.py:
Changed the way the extra template parameters are specified. MIPS might need to be adjusted.
src/arch/sparc/isa/decoder.isa:
Changed how Frd_N was set up.
src/arch/sparc/isa/formats/blockmem.isa:
Fixed up handling of block memory operations
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem.isa:
src/arch/sparc/isa/formats/priv.isa:
Fix up extra template parameters.
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relied on implementation specific behavior, namely right shifting a signed value.
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src/arch/sparc/isa/bitfields.isa:
Added a field to retrieve the asi from the ExtMachInst
src/arch/sparc/isa/decoder.isa:
Fixed up how the size of memory operations where handled, and use the new EXT_ASI bit field.
src/arch/sparc/isa/formats.isa:
add includes for the new formats.
src/arch/sparc/isa/formats/basic.isa:
Add a template for BasicDecodeWithMnemonic which is needed by the unimp format.
src/arch/sparc/isa/formats/mem.isa:
Change around the memory format to figure out the memory access width on its own.
src/arch/sparc/isa/operands.isa:
Added support for the operands of block loads/stores which are offset from Frd.
src/arch/sparc/utility.hh:
Encoded the ASI into the ExtMachInst
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This takes advantage of microcode.
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Alpha
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extra : convert_revision : 7e26053696b23fbc0b8cd5827a5072dcf2526e2b
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
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Fix a segfault associated with DefaultId
src/mem/bus.cc:
Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
Make the Default ID more unique (it overlapped with Broadcast ID)
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src/mem/bus.cc:
Add debugging statement
src/mem/bus.hh:
Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
Rework timing port to retry properly
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src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 70187b8f04d0f8424512f64bdade05bf1aca85a3
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Fix bug with deadlocking
src/mem/cache/base_cache.cc:
Make sure to not wait anymore
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extra : convert_revision : 5f7b44a1c475820b9862275a0d6113ec2991735d
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case as well when dealing with grants that aren't used.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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some reason.
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src/mem/cache/base_cache.cc:
When turning asserts into if's don't forget to invert.
Must be too sleepy.
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extra : convert_revision : ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
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uprgades to owned blocks hit in the WB buffer
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
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extra : convert_revision : eaae105025635c37af06cf72bb061ce82def9dc9
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src/base/traceflags.py:
Add new flags for cacheport
src/mem/bus.cc:
Add debugging info
src/mem/cache/base_cache.cc:
Add debuggin info
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extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
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try to send another packet while it's still waiting for the bus.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 7b7a1b03ffed36bce49595962ea57c08d1d1a4ad
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src/mem/cache/base_cache.cc:
Add sanity checks
src/mem/cache/base_cache.hh:
Fix for retry mechanism
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extra : convert_revision : 9298e32e64194b1ef3fe51242595eaa56dcbbcfd
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src/mem/tport.cc:
minor formatting tweak
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : aa59d3169d84bcd13b8c97f22b52aeef43dc33c3
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Update retry mechanism
src/mem/cache/base_cache.cc:
Rework the retry mechanism
src/mem/cache/base_cache.hh:
Rework the retry mechanism
Try to fix memory bug
src/mem/cache/cache_impl.hh:
Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
Fix mem leak on writebacks
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extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : 4036e8447fb3038d93285c6582900210d7d88d67
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Fix Upgrades being blocked by slave
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : 6027c395af044858465eafd3ea78bcfe4c923bcc
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/packet.hh:
Hand merge code
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extra : convert_revision : d659418f24f4f4bf9867fec8573a5d227c0dfcea
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configs/common/SysPaths.py:
Undo accidental change.
src/SConscript:
Fix.
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extra : convert_revision : 665b186cff7d8ae560601ced7ae407a41a16cfea
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src/mem/cache/base_cache.cc:
Fix a bug about not having a request to send
src/mem/cache/base_cache.hh:
Fix a bug with the blocking code
src/mem/cache/cache.hh:
AFix a bug with snoop hits in WB buffer
src/mem/cache/cache_impl.hh:
Fix a bug with snoop hits in WB buffer
Also, add better DPRINTF's
src/mem/cache/miss/miss_queue.cc:
Fix a bug with upgrades (Need to clean it up later)
src/mem/cache/miss/mshr.cc:
Fix a memory leak bug, still some outstanding with writebacks not being deleted
src/mem/cache/miss/mshr_queue.cc:
Fix a bug about upgrades (need to clean up later)
src/mem/packet.hh:
Fix for newly added cmd attribute for upgrades
tests/configs/memtest.py:
More interesting testcase
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packet was waiting for the bus.
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src/mem/bus.cc:
Put back the check to see if the bus is busy. Also, populate the fields in the packet to indicate when the first word and the entire packet will be delivered.
src/mem/bus.hh:
Remove the occupyBus function.
src/mem/packet.hh:
Added fields to the packet to indicate when the first chunk of a packet arrives, and when the entire packet arrives.
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.
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extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
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src/cpu/o3/cpu.cc:
Comment out reseting CPU structures for now. This can be updated to work in the future.
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extra : convert_revision : bc1a86e2fe47da5acb14ba8b64568b0355431f1c
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Not fully implemented yet, but good enough for single level cache coherence
src/mem/packet.hh:
Add a bit to distinguish invalidates and upgrades
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extra : convert_revision : 5bf50d535857cea37fbdaf7993915d1332cb757e
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : 9158d81231cd1d083393576744ce80afd0b74867
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Remove some dead code.
src/mem/cache/cache_impl.hh:
Upgrades don't need a response.
Moved satisfied check into bus so removed some dead code.
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/packet.hh:
Upgrades don't require a response
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