index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
Age
Commit message (
Expand
)
Author
2014-03-03
kvm: Initialize signal handlers from startupThread()
Andreas Sandberg
2014-03-01
ruby: message buffer: changes related to tracking push/pop times
Nilay Vaish
2014-03-01
ruby: make the max_size variable of the MessageBuffer unsigned
Nilay Vaish
2014-03-01
cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPU
Christopher Torng
2014-03-01
ruby: profiler: statically allocate stats variable
Nilay Vaish
2014-02-23
ruby: route all packets through ruby port
Nilay Vaish
2014-02-23
ruby: Simplify RubyPort flow control and routing
Andreas Hansson
2014-02-23
ruby: message buffer: refactor code
Nilay Vaish
2014-02-23
ruby: remove few not required #includes
Nilay Vaish
2014-02-23
ruby: slicc: remove unused COPY_HEAD functionality
Nilay Vaish
2014-02-23
ruby: protocols: remove unused action z_stall
Nilay Vaish
2014-02-21
ruby: network: move message buffers to base network class.
Nilay Vaish
2014-02-21
ruby: network: garnet: fixed: removes net_ptr from links
Nilay Vaish
2014-02-21
ruby: cache: remove not required variable m_cache_name
Nilay Vaish
2014-02-20
ruby: network: garnet: fixed: removes next cycle functions
Nilay Vaish
2014-02-20
ruby: controller: slight code refactoring
Nilay Vaish
2014-02-20
ruby: mesi three level: rename incorrectly named files
Nilay Vaish
2014-02-20
ruby: network: removes unused code.
Nilay Vaish
2014-02-20
ruby: slicc: slight code refactoring
Nilay Vaish
2014-02-20
ruby: message buffer: removes some unecessary functions.
Nilay Vaish
2014-02-20
kvm: Add support for multi-system simulation
Andreas Sandberg
2014-02-18
mem: Fix bug in PhysicalMemory use of mmap and munmap
Andreas Hansson
2014-02-18
dev: Include basic devices in NULL ISA build
Andreas Hansson
2014-02-18
mem: Filter cache snoops based on address ranges
Andreas Hansson
2014-02-18
mem: Add a wrapped DRAMSim2 memory controller
Andreas Hansson
2014-02-18
mem: Fix input to DPRINTF in CommMonitor
Andreas Hansson
2014-02-09
cpu: simple: Add support for using branch predictors
Andreas Sandberg
2014-02-06
base: calls abort() from fatal
Nilay Vaish
2014-02-06
ruby: memory controller: use MemoryNode *
Nilay Vaish
2014-02-05
x86: Fix x87 state transfer bug
Andreas Sandberg
2014-02-02
x86, kvm: Fix bug in the RFlags get and set functions
Nikos Nikoleris
2014-01-30
unittest: Fix build errors
Ola Jeppsson
2014-01-29
mem: Add additional tolerance to stride prefetcher
Mitch Hayenga
2014-01-29
mem: Allowed tagged instruction prefetching in stride prefetcher
Mitch Hayenga
2014-01-29
mem: prefetcher: add options, support for unaligned addresses
Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-29
cpu: fix bug when TrafficGen deschedules event
Xiangyu Dong
2014-01-28
arm: Enable umask syscall in SE mode
Mitch Hayenga
2014-01-28
base: Fix race condition in the socket listen function
Mitch Hayenga
2014-01-28
mem: Remove redundant findVictim() input argument
Amin Farmahini
2014-01-28
mem: Fixes a bug in simple_dram write merging
Amin Farmahini
2014-01-27
x86: use lfpimm instead of limm for fptan
Nilay Vaish
2014-01-27
x86: implements x87 add/sub instructions
Nilay Vaish
2014-01-27
x86: implements fxch instruction.
Nilay Vaish
2014-01-27
x86: correct error in emms instruction.
Nilay Vaish
2014-01-24
arm: Add support for ARMv8 (AArch64 & AArch32)
ARM gem5 Developers
2014-01-24
arch: Make all register index flattening const
Andreas Hansson
2014-01-24
checker: CheckerCPU handling of MiscRegs was incorrect
Geoffrey Blake
2014-01-24
arch, cpu: Add support for flattening misc register indexes.
Ali Saidi
2014-01-24
cpu: Add support for Memory+Barrier instruction types in O3 cpu.
Giacomo Gabrielli
2014-01-24
cpu: Add support for instructions that zero cache lines.
Ali Saidi
[next]