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AgeCommit message (Expand)Author
2019-01-17cpu-o3: Make the smtLSQPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtFetchPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17python: Add support for scoped enumsNikos Nikoleris
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-16arch: Make the ISA register types aliases for the global types.Gabe Black
2019-01-16arm: Make the fp register types 64 bits.Gabe Black
2019-01-16mem-cache: Access Map Pattern Matching PrefetcherJavier Bueno
2019-01-16mem-cache: Signature Path PrefetcherJavier Bueno
2019-01-16mem-cache: allow prefetchers to emit page crossing referencesJavier Bueno
2019-01-16mem-cache: virtual address support for prefetchersJavier Bueno
2019-01-16arch-arm: Read VMPIDR instead of MPIDR when EL2 is EnabledGiacomo Travaglini
2019-01-16arch-arm: Added TLBI_ALL EL2 instructionAnouk Van Laer
2019-01-16arch-riscv: Add interrupt handlingAlec Roelke
2019-01-16arch-riscv: Fix reset function and styleAlec Roelke
2019-01-15cpu: Fix usage of setArchVecElemGiacomo Travaglini
2019-01-15arch-arm: Fix usage of RegId constructor for VecElemGiacomo Travaglini
2019-01-14arm: Stop using the FloatReg and FloatRegBits types.Gabe Black
2019-01-14config: De-nest the code in Port.splice().Gabe Black
2019-01-14config: Fix an error message in Port.splice().Gabe Black
2019-01-11misc: updated shabang for python scriptAndrea Mondelli
2019-01-10sim-se, arch-arm: Add support for getdents64Javier Setoain
2019-01-10arch-arm, sim-se: Add support for TLS in cloneAndreas Sandberg
2019-01-10arch-arm, sim-se: Fix incorrect SP handling in cloneAndreas Sandberg
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
2019-01-10sim-se: Correctly calculate next PC in cloneAndreas Sandberg
2019-01-10sim-se: Use CONFIG_CLONE_BACKWARDS for ArmAndreas Sandberg
2019-01-10arch-arm, sim-se: Wire up syscalls needed for pthreadsJavier Setoain
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
2019-01-10base: Make it possible to convert strings to enumsGiacomo Travaglini
2019-01-10systemc: Fix a function which was broken during style fixes.Gabe Black
2019-01-09arch-arm: Additional bits in misc ARM registers to use with the TLB and page ...Ivan Pizarro
2019-01-09systemc: Make input.txt a dependency for the tlm/endian_conv test.Gabe Black
2019-01-09systemc: Exclude some failing systemc TLM tests in working.filt.Gabe Black
2019-01-09systemc: Remove the TLM dependence on a non-standard method.Gabe Black
2019-01-09systemc: Stop using the sc_string_view type.Gabe Black
2019-01-09systemc: Replace sc_core::sc_type_index with std::type_index.Gabe Black
2019-01-09systemc: Stop using the Accellera specific "none" global event object.Gabe Black
2019-01-09systemc: Rename tlm_core header files to have a .hh extentension.Gabe Black
2019-01-09systemc: Add a dummy argv[0] when running the tests.Gabe Black
2019-01-09systemc: Stop using the non-standard sc_time % in TLM.Gabe Black
2019-01-09systemc: Add an elaboration_done method to sc_simcontext.Gabe Black
2019-01-09systemc: Include cstring in the tlm header file.Gabe Black
2019-01-09systemc: Remove redundant tlm_ prefixes from file names.Gabe Black
2019-01-09systemc: Replace some calls to some Accellera specific functions in TLM.Gabe Black
2019-01-09systemc: Rename tlm .cpp files to .cc and add SConscripts.Gabe Black
2019-01-09systemc: Fix style issues in the TLM header files.Gabe Black
2019-01-09systemc: Also look for tests in the tlm test directory.Gabe Black
2019-01-09systemc: Initial import of TLM headers from Accellera.Gabe Black
2019-01-07scons: Disable partial linking on Mac OSNikos Nikoleris