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2013-11-01sim: Clarify the difference between tracing and debuggingAndreas Hansson
This patch changes the name the command-line options related to debug output to all start with "debug" rather than being a mix of that and "trace". It also makes it clear that the breakpoint time is specified in ticks and not in cycles.
2013-10-31ARM: add support for TEEHBR accessChander Sudanthi
Thumb2 ARM kernels may access the TEEHBR via thumbee_notifier in arch/arm/kernel/thumbee.c. The Linux kernel code just seems to be saving and restoring the register. This patch adds support for the TEEHBR cp14 register. Note, this may be a special case when restoring from an image that was run on a system that supports ThumbEE.
2013-10-31dev: Add 'OSC' oscillator sys control reg support to VersatileExpressMatt Evans
The VE motherboard provides a set of system control registers through which various motherboard and coretile registers are accessed. Voltage regulators and oscillator (DLL/PLL) config are examples. These registers must be impleted to boot Linux 3.9+ kernels.
2013-10-31dev: Add support for MSI-X and Capability Lists for ARM and PCI devicesGeoffrey Blake
This patch adds the registers and fields to the PCI device to support Capability lists and to support MSI-X in the GIC.
2013-10-31dev: Fix race conditions in IDE device on newer kernelsGeoffrey Blake
Newer linux kernels and distros exercise more functionality in the IDE device than previously, exposing 2 races. The first race is the handling of aborted DMA commands would immediately report the device is ready back to the kernel and cause already in flight commands to assert the simulator when they returned and discovered an inconsitent device state. The second race was due to the Status register not being handled correctly, the interrupt status bit would get stuck at 1 and the driver eventually views this as a bad state and logs the condition to the terminal. This patch fixes these two conditions by making the device handle aborted commands gracefully and properly handles clearing the interrupt status bit in the Status register.
2013-10-31base: Add support for ipv6 into inet.hh/inet.ccGeoffrey Blake
2013-10-31cpu: Construct ROB with cpu params struct instead of each variableFaissal Sleiman
Most other structures/stages get passed the cpu params struct.
2013-10-31config: Fix handling of parents for simobject vectorsGeoffrey Blake
SimObjectVector objects did not provide the same interface to the _parent attribute through get_parent() like a normal SimObject. It also handled assigning a _parent incorrectly if objects in a SimObjectVector were changed post-creation, leading to errors later when the simulator tried to execute. This patch fixes these two omissions.
2013-10-31sim: added option to serialize SimLoopExitEventDam Sunwoo
SimLoopExitEvents weren't serialized by default. Some benchmarks utilize a delayed m5 exit pseudo op call to terminate the simulation and this event was lost when resuming from a checkpoint generated after the pseudo op call. This patch adds the capability to serialize the SimLoopExitEvents and enable serialization for m5_exit and m5_fail pseudo ops by default. Does not affect other generic SimLoopExitEvents.
2013-10-31mem: Add "const" attribute to Packet gettersStephan Diestelhorst
Add a "const" keywords to the getters in the Packet class so these can be invoked on const Packet objects.
2013-10-31mem: Add privilege info to request classPrakash Ramrakhyani
This patch adds a flag in the request class that indicates if the request was made in privileged mode.
2013-10-31cpu: Fix O3 issuse with load+barrier instructions.Ali Saidi
Fix a problem in the O3 CPU for instructions that are both memory loads and memory barriers (e.g. load acquire) and to uncacheable memory. This combination can confuse the commit stage into commitng an instruction that hasn't executed and got it's value yet. At the same time refactor the code slightly to remove duplication between two of the cases.
2013-10-30ruby: set SenderMachine in messages of MOESI_CMP_directoryLluc Alvarez
This patch adds missing initializations of the SenderMachine field of out_msg's when thery are created in the L2 cache controller of the MOESI_CMP_directory coherence protocol. When an out_msg is created and this field is left uninitialized, it is set to the default value MachineType_NUM. This causes a panic in the MachineType_to_string function when gem5 is executed with the Ruby debug flag on and it tries to print the message. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-10-30ruby: Fixed a deadlock when restoring a checkpoint with garnetEmilio Castillo
This patch fixes a problem where in Garnet, the enqueue time in the VCallocator and the SWallocator which is of type Cycles was being stored inside a variable with int type. This lead to a known problem restoring checkpoints with garnet & the fixed pipeline enabled. That value was really big and didn't fit in the variable overflowing it, therefore some conditions on the VC allocation stage & the SW allocation stage were not met and the packets didn't advance through the network, leading to a deadlock panic right after the checkpoint was restored. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-10-17mem: De-virtualise interfaces in the CoherentBusStephan Diestelhorst
The CoherentBus eventually got virtual methods for its interface. The "virtuality" of the CoherentBus, however, comes already from the virtual interface of the bus' ports. There is no need to add another layer of virtual functions, here.
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-17mem: Add PortID to QueuedMasterPort constructorSascha Bischoff
This patch adds the PortID to the QueuedMasterPort. This allows a PortID to be specified as it previously was set to the detault value of -1.
2013-10-17arm: Add a 'clear PPI' method to gic_pl390Matt Evans
The underlying assumption that all PPIs must be edge-triggered is strained when the architected timers and VGIC interfaces make level-behaviour observable. For example, a virtual timer interrupt 'goes away' when the hypervisor is entered and the vtimer is disabled; this requires a PPI to be de-activated. The new method simply clears the interrupt pending state.
2013-10-17config: Fix ommission of number base in ethernet address paramGeoffrey Blake
The ethernet address param tries to convert a hexadecimal string using int() in python, which defaults to base 10, need to specify base 16 in this case.
2013-10-17config: Fix for port references generated multiple timesGeoffrey Blake
SimObjects are expected to only generate one port reference per port belonging to them. There is a subtle bug with using "not" here as a VectorPort is seen as not having a reference if it is either None or empty as per Python docs sec 9.9 for Standard operators. Intended behavior is to only check if we have not created the reference.
2013-10-17dev: Add option to disable framebuffer .bmp dump in run folderDam Sunwoo
There is an option to enable/disable all framebuffer dumps, but the last frame always gets dumped in the run folder with no other way to disable it. These files can add up very quickly running many experiments. This patch adds an option to disable them. The default behavior remains unchanged.
2013-10-17cpu: Removing an unused variable in renameFaissal Sleiman
2013-10-17cpu: Change IEW DPRINTF to use IEW debug flagFaissal Sleiman
IEW DPRINTF uses Decode debug flag, which appears to be a copying error. This patch changes this to the IEW Debug flag.
2013-10-17cpu: Put in assertions to check for maximum supported LQ/SQ sizeFaissal Sleiman
LSQSenderState represents the LQ/SQ index using uint8_t, which supports up to 256 entries (including the sentinel entry). Sending packets to memory with a higher index than 255 truncates the index, such that the response matches the wrong entry. For instance, this can result in a deadlock if a store completion does not clear the head entry.
2013-10-17arm: Accomodate function name changes in newer linux kernelsEric Van Hensbergen
2013-10-17arm: Fix a GIC mask register bugAli Saidi
This resulted in a kernel printk that said, "GIC CPU mask not found - kernel will fail to boot."
2013-10-17cpu: Fix O3 uncacheable load that is replayed but misses the TLBAli Saidi
This change fixes an issue in the O3 CPU where an uncachable instruction is attempted to be executed before it reaches the head of the ROB. It is determined to be uncacheable, and is replayed, but a PanicFault is attached to the instruction to make sure that it is properly executed before committing. If the TLB entry it was using is replaced in the interveaning time, the TLB returns a delayed translation when the load is replayed at the head of the ROB, however the LSQ code can't differntiate between the old fault and the new one. If the translation isn't complete it can't be faulting, so clear the fault.
2013-10-17mem: Make MemoryAccess flag more verboseAli Saidi
This patch extends the MemoryAccess debug flag to report who sent the requests and the cacheability.
2013-10-17build: Place proto output in the same directory, also for EXTRASAndreas Hansson
This patch changes the ProtoBuf builder such that the generated source and header is placed in the build directory of the proto file. This was previously not the case for the directories included as EXTRAS. To make this work, we also ensure that the build directory for the EXTRAS are added to the include path (which does not seem to automatically be the case).
2013-10-17dev: Allow additional UART interrupts to be setAli Saidi
This patch allows setting a few additional interrupts for status changes that should never occur.
2013-10-16kvm: Fix latency calculation of IPR accessesAndreas Sandberg
When handling IPR accesses in doMMIOAccess, the KVM CPU used clockEdge() to convert between cycles and ticks. This is incorrect since doMMIOAccess is supposed to return a latency in ticks rather than when the access is done. This changeset fixes this issue by returning clockPeriod() * ipr_delay instead.
2013-10-15ruby: eliminate non-determinism from ruby.stats outputSteve Reinhardt
Get rid of non-deterministic "stats" in ruby.stats output such as time & date of run, elapsed & CPU time used, and memory usage. These values cause spurious miscomparisons when looking at output diffs (though they don't affect regressions, since the regressions pass/fail status currently ignores ruby.stats entirely). Most of this information is already captured in other places (time & date in stdout, elapsed time & mem usage in stats.txt), where the regression script is smart enough to filter it out. It seems easier to get rid of the redundant output rather than teaching the regression tester to ignore the same information in two different places.
2013-10-15arch/x86: add support for explicit CC register fileYasuko Eckert
Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch.
2013-10-15cpu: add a condition-code register classYasuko Eckert
Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
2013-10-15cpu/o3: clean up rename map and free listSteve Reinhardt
Restructured rename map and free list to clean up some extraneous code and separate out common code that can be reused across different register classes (int and fp at this point). Both components now consist of a set of Simple* objects that are stand-alone rename map & free list for each class, plus a Unified* object that presents a unified interface across all register classes and then redirects accesses to the appropriate Simple* object as needed. Moved free list initialization to PhysRegFile to better isolate knowledge of physical register index mappings to that class (and remove the need to pass a number of parameters to the free list constructor). Causes a small change to these stats: cpu.rename.int_rename_lookups cpu.rename.fp_rename_lookups because they are now categorized on a per-operand basis rather than a per-instruction basis. That is, an instruction with mixed fp/int/misc operand types will have each operand categorized independently, where previously the lookup was categorized based on the instruction type.
2013-10-15cpu: rename *_DepTag constants to *_Reg_BaseSteve Reinhardt
Make these names more meaningful. Specifically, made these substitutions: s/FP_Base_DepTag/FP_Reg_Base/g; s/Ctrl_Base_DepTag/Misc_Reg_Base/g; s/Max_DepTag/Max_Reg_Index/g;
2013-10-15isa: clean up register constantsSteve Reinhardt
Clean up and add some consistency to the *_Base_DepTag constants as well as some related register constants: - Get rid of NumMiscArchRegs, TotalArchRegs, and TotalDataRegs since they're never used and not always defined - Set FP_Base_DepTag = NumIntRegs when possible (i.e., every case except x86) - Set Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs (this was true before, but wasn't always expressed that way) - Drastically reduce the number of arbitrary constants appearing in these calculations
2013-10-15cpu/o3: clean up scoreboard objectSteve Reinhardt
It had a bunch of fields (and associated constructor parameters) thet it didn't really use, and the array initialization was needlessly verbose. Also just hardwired the getReg() method to aleays return true for misc regs, rather than having an array of bits that we always kept marked as ready.
2013-10-15cpu/o3: clean up physical register fileSteve Reinhardt
No need for PhysRegFile to be a template class, or have a pointer back to the CPU. Also made some methods for checking the physical register type (int vs. float) based on the phys reg index, which will come in handy later.
2013-10-15cpu/inorder: merge register class enumsSteve Reinhardt
The previous patch introduced a RegClass enum to clean up register classification. The inorder model already had an equivalent enum (RegType) that was used internally. This patch replaces RegType with RegClass to get rid of the now-redundant code.
2013-10-15cpu: clean up architectural register classificationSteve Reinhardt
Move from a poorly documented scheme where the mapping of unified architectural register indices to register classes is hardcoded all over to one where there's an enum for the register classes and a function that encapsulates the mapping.
2013-10-15mem: Rename the ASI_BITS flag field in RequestAndreas Sandberg
ASI_BITS in the Request object were originally used to store a memory request's ASI on SPARC. This is not the case any more since other ISAs use the ASI bits to store architecture-dependent information. This changeset renames the ASI_BITS to ARCH_BITS which better describes their use. Additionally, the getAsi() accessor is renamed to getArchFlags().
2013-10-15mem: Use a flag instead of address bit 63 for generic IPRsAndreas Sandberg
Using address bit 63 to identify generic IPRs caused problems on SPARC, where IPRs are heavily used. This changeset redefines how generic IPRs are identified. Instead of using bit 63, we now use a separate flag (GENERIC_IPR) a memory request.
2013-10-07x86: enables lstat and readlink syscallsNilay Vaish
2013-10-07base: Fix a potential race in PollQueue::setupAsyncIOAndreas Sandberg
There is a potential race between enabling asynchronous IO and selecting the target for the SIGIO signal. This changeset move the F_SETOWN call to before the F_SETFL call that enables SIGIO delivery. This ensures that signals are always sent to the correct process.
2013-10-03kvm: Service events in the instruction event queuesAndreas Sandberg
This changset adds calls to the service the instruction event queues that accidentally went missing from commit [0063c7dd18ec]. The original commit only included the code needed to schedule instruction stops from KVM and missed the functionality to actually service the events.
2013-09-30x86: Add support for m5ops through a memory mapped interfaceAndreas Sandberg
In order to support m5ops in virtualized environments, we need to use a memory mapped interface. This changeset adds support for that by reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR interface for m5ops. The mapping is done in the X86ISA::TLB::finalizePhysical() which means that it just works for all of the CPU models, including virtualized ones.
2013-09-30arch: Add support for m5ops using mmapped IPRsAndreas Sandberg
In order to support m5ops on virtualized CPUs, we need to either intercept hypercall instructions or provide a memory mapped m5ops interface. Since KVM does not normally pass the results of hypercalls to userspace, which makes that method unfeasible. This changeset introduces support for m5ops using memory mapped mmapped IPRs. This is implemented by adding a class of "generic" IPRs which are handled by architecture-independent code. Such IPRs always have bit 63 set and are handled by handleGenericIprRead() and handleGenericIprWrite(). Platform specific impementations of handleIprRead and handleIprWrite should use GenericISA::isGenericIprAccess to determine if an IPR address should be handled by the generic code instead of the architecture-specific code. Platforms that don't need their own IPR support can reuse GenericISA::handleIprRead() and GenericISA::handleIprWrite().
2013-09-30x86: Add support for FXSAVE, FXSAVE64, FXRSTOR, and FXRSTOR64Andreas Sandberg
2013-09-30x86: Add support for FLDENV & FNSTENVAndreas Sandberg