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2019-01-09systemc: Remove the TLM dependence on a non-standard method.Gabe Black
The sc_event_finder class in Accellera's implementation has a non-standard report_error function that it uses internally. The TLM headers were calling that function in their own event finder subclass. This change replaces that call with what should be an equivalent bit of code which is based on the report_error implementation. Change-Id: Id57d26791df01403a77e70d5f4a00f650dc33599 Reviewed-on: https://gem5-review.googlesource.com/c/15063 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Stop using the sc_string_view type.Gabe Black
It doesn't seem to provide anything more that std::string, and comes with extra dependencies/baggage. Change-Id: I2c599bcc93fa4a944ff249410d24e8f8be981afe Reviewed-on: https://gem5-review.googlesource.com/c/15298 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Replace sc_core::sc_type_index with std::type_index.Gabe Black
The former is either the same as the later, or a custom wrapper if C++11 isn't supported. Since we generally expect C++11 support, we can skip the indirection. Change-Id: I9a45e3854bb7cc56d094e3fe2773fe4b5c94403b Reviewed-on: https://gem5-review.googlesource.com/c/15297 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Stop using the Accellera specific "none" global event object.Gabe Black
That event being available is nonstandard. Define our own static event for use in that case. Change-Id: I5e8892bd83cc1984d63949ef3e249755dca0c702 Reviewed-on: https://gem5-review.googlesource.com/c/15296 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Rename tlm_core header files to have a .hh extentension.Gabe Black
This makes those files more consistent with other headers in gem5. The top level headers (tlm and tlm.h) and the tlm_utils headers were left alone since the user might reasonably expect those to have a well known name. The tlm_core headers by comparison are an implementation detail, and users shouldn't include them directly by name. Change-Id: Ibc82e8159e47717c79d76f50ed96fdd619294a06 Reviewed-on: https://gem5-review.googlesource.com/c/15067 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Add a dummy argv[0] when running the tests.Gabe Black
One TLM test will complain if argc isn't 1 or 2, assuming that that must mean that argc > 2. If it's 0 then the test will also complain and fail. We therefore need to pass it at least a dummy value in argv/argc. Change-Id: I5c64856f46d1459d7238e88ad8ba06933c7c38b8 Reviewed-on: https://gem5-review.googlesource.com/c/15065 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Stop using the non-standard sc_time % in TLM.Gabe Black
The TLM headers were using the non-standard % operator on sc_time. This change replaces that with % applied to the result of sc_time::value(). Change-Id: Ic381eb1ada2c994d04e65896db178f58446944ae Reviewed-on: https://gem5-review.googlesource.com/c/15062 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Add an elaboration_done method to sc_simcontext.Gabe Black
The TLM headers rely on this non-standard function. Change-Id: Iaedec35f1f363dcf3e1fcdb58a74eb2cdc05ddc0 Reviewed-on: https://gem5-review.googlesource.com/c/15061 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Include cstring in the tlm header file.Gabe Black
A lot of TLM implementation assumes the string functions (memcpy, memset, etc) are available, but don't include cstring. Lets do that for them to avoid having to fix up a lot of places. Change-Id: I1f26d3a227fe2cefc2613e24cbb0333216e46ee9 Reviewed-on: https://gem5-review.googlesource.com/c/15060 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Remove redundant tlm_ prefixes from file names.Gabe Black
We already know those files belong to tlm because of the directory they're in. Removing the prefix makes the paths of the headers less enormously long. Change-Id: I869e58fae904162f353bb31f4c0919fba08dffa6 Reviewed-on: https://gem5-review.googlesource.com/c/15059 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Replace some calls to some Accellera specific functions in TLM.Gabe Black
The TLM event finder class was calling implementation specific functions from the Accellera version of systemc. This change replaces those calls with equivalent calls which match the gem5 implementation. Change-Id: I0ecdb0a4bf09aeb1aad823a01105fbd88edb4601 Reviewed-on: https://gem5-review.googlesource.com/c/15075 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Rename tlm .cpp files to .cc and add SConscripts.Gabe Black
Change-Id: Ia30192b441dd34bc7165c6335386c88c0015fdf6 Reviewed-on: https://gem5-review.googlesource.com/c/15295 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Fix style issues in the TLM header files.Gabe Black
Change-Id: Id12ffb9b56b3887afcf30120f81ce5eb75a5987b Reviewed-on: https://gem5-review.googlesource.com/c/15057 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Also look for tests in the tlm test directory.Gabe Black
Both basic systemc and tlm tests were present, but scons only looked in the systemc directory when populating the test json. This change makes it also look in the tlm directory so that those tests can be run. Change-Id: Id65b744664350f6105fb3a4f28cbc7ab91d8c82e Reviewed-on: https://gem5-review.googlesource.com/c/15056 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Initial import of TLM headers from Accellera.Gabe Black
These headers will need to be cleaned up and have some Accellera specific quirks ironed out of them, but I'll do that in a later change to make it clear what those changes are. Change-Id: Ia4e08633ab552b4c616c66c9b7e2bbd78ebfe7b9 Reviewed-on: https://gem5-review.googlesource.com/c/15055 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-07scons: Disable partial linking on Mac OSNikos Nikoleris
Up until Apple LLVM version 10.0.0 (clang-1000.11.45.5), partial linked objects do not expose symbols that are marked with the hidden visibility and consequently building gem5 on Mac OS fails. As a workaround, we disable partial linking, however, we may want to revisit in the future. Change-Id: I0a26dae082bf723c2bd49d90e4497e44ecab9c41 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15235 Reviewed-by: Andrea Mondelli <andrea.mondelli@ucf.edu> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-04dev, arm: Warn on PL011 DMA disableJan-Peter Larsson
The PL011 spec specifies a DMACR register at offset 0x48, which isn't implemented in the model. Currently any attempt to access the register results in a panic. This change swaps the panic for a warning only when software writes into DMACR to disable DMA, keeping the panic otherwise. Change-Id: I04586b52df8d5d174536276fd7ae19e77ff4681a Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15279 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Added VGIC GICV_IIDR responseAnouk Van Laer
Change-Id: I60e8eadbbbf07c0f8b726213fd580aeb0dd0e00b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15278 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Implement GIC-400 model from GicV2Giacomo Travaglini
Implementation registers for the GICv2 model currently hold values referring to a GIC-400 implementation. This patch is making them parametrizable so that it is possible to instantiate a GIC-400 model. The patch is also modifying Realview platform to use new GIC-400 model in lieau of GICv2. Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15277 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Move VGic from Realview.py to Gic.pyGiacomo Travaglini
Change-Id: I17f2fb6be2435d4601263e7f68a0582e0cc70838 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15276 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Added unimplemented GICv2 GICC_DIRAnouk Van Laer
This GICC CPU register is not implemented but just gives a warning. Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15275 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-03arm: properly handle RES0/1 for SCTLRsCurtis Dunham
They were being treated as RAZ/RAO, which is incorrect. Put the access masks in the register metadatabase now that we have one. Also fix this for HVBAR. Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/10401 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-12-22cpu: Stop using unions to store FP registers.Gabe Black
These are now accessed only as integer values. Change-Id: I21ae6537ebbcbaa02890384194ee1ce001c092bb Reviewed-on: https://gem5-review.googlesource.com/c/14458 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-20arch, cpu: Remove float type accessors.Gabe Black
Use the binary accessors instead. Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2 Reviewed-on: https://gem5-review.googlesource.com/c/14457 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-19arch-arm: Add Crypto in SE modeGiacomo Travaglini
This patch is also enabling AArch32 crypto instructions by setting the ID_ISAR5 register accordingly. Change-Id: Id412585b39b78570a65bd3047199c84e9db76cda Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15155 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-12-19systemc: Allow specific functions to shadow the base class methodNikos Nikoleris
sc_in::bind and sc_core::sc_object::print shadow their respective base class method. This change adds the necessary declarations to inform the compiler that this is intentional. Change-Id: I8c6bc0f05aa568630783db63d52be90f4ea4748c Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15135 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-19scons: Disable systemc on Mac OSNikos Nikoleris
LLVM on Mac OS up until version 10.0.0 doesn't seem to support the attribute for weak linking and fails to compile. Additionally, even the basic example tests fail. Therefore, this change disables systemc by default on Mac OS until we address these issues. Change-Id: Iaa6360ec61317e01f4e645af8b509961b3144282 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14818 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-18arch: Make the ISA parser always use binary floating point accessors.Gabe Black
Any operands which use read_code or write_code would need to start using the floatToBits and bitsToFloat, but only ARM is using that mechanism, and not on float operands. Also I notice that the "predicate" mechanism for operands ignores the read_code and write_code mechanism, and using both will not work correctly. This change makes no attempt to fix that problem, but shouldn't contribute to it either. Change-Id: I0e3a7f78ed28f40cb66958ef12c32e862950fde0 Reviewed-on: https://gem5-review.googlesource.com/c/14456 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-18systemc: Ensure resets and edges are notified when signaling a change.Gabe Black
Boolean sc_buffers (either pure bool or sc_dt::sc_logic) should signal positive and negative edges and resets even when their value doesn't change, unlike sc_signals. The spec doesn't actually say that and just mentions the value changed event, but it may have been implied that the other types of events also happen, they just made special mention of the value change event. This change moves some code around a bit so that when _signalChange() is called, if the underlying type is a boolean signal, it will automatically notify the appropriate edge event and signal any reset. Putting the functionality in _signalChange instead of delegating it to the sc_buffer lets us have a single template for sc_buffer and makes the base class template specialization handle whether the edge events exist, and if so which should be notified. Change-Id: Ic4ca86afc3fde6a9df5c15a0a7386e24ac89a9e2 Reviewed-on: https://gem5-review.googlesource.com/c/14916 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-11cpu: Fixed typos in parameter/stats descriptionsPau Cabre
Change-Id: I7b3274a3e37128da35f497da150af08343e97ee6 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14795 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-12-11cpu: Added parameters to enable/disable features in LTAGEPau Cabre
They are for the following features in the LTAGE loop predictor: - Hashing for calculating the loop table entry - Add direction information - Add speculative iteration number information Change-Id: I395f4526163ee0d0229d1e87cde2bb046f1dd43a Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14597 Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Louis Delhez <ldelhez@ucla.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-12-11cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctorTony Gutierrez
Change 9af1214 added a new ctor to the LSQUnit, however there is a typo/bug because it sizes the SQEntries member variable to lqEntries + 1, as opposed to sqEntries + 1. This change corrects the issue by using sqEntries. Change-Id: I19dfaa5c0e335bd7b84343a92034147d7c5d914e Reviewed-on: https://gem5-review.googlesource.com/c/15015 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-12-10systemc: Update test output for longer lived processes.Gabe Black
In the systemc spec, process handles can be invalidated if they have no children and are terminated. The implementation is not required to do so however, and for the sake of simplicity gem5 currently does not. To quote: "When the underlying process instance terminates, if the process instance has no surviving children, an implementation may choose to invalidate any associated process handles, but it is not obliged to do so." Two tests have reference output which is affected by this (legal) difference in behavior. In one case, the test creates new processes which reuse the names of processes that have been terminated. Since gem5 doesn't invalidate the old processes, a standard mechanism is activated which renames the processes to something which is unique. The other test has this same problem, and also prints the hierarchy of processes several times during the test. In that hierarchy, the terminated tests with no live children are still present, where in the old reference output they've been removed. This change updates the reference output to match gem5's behavior. Change-Id: I363448de10080bdce01a4df92f991c67b31a2401 Reviewed-on: https://gem5-review.googlesource.com/c/14919 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-10systemc: Update the ordering in the reference output for some tests.Gabe Black
There are a number of cases where systemc leaves the decision of what order things happen up to the kernel, and any ordering is legal and conformant with the spec as long as it's repeatable. The reference outputs reflect a particular choice of ordering which is implementation specific, and while considerable effort has been made to make the gem5 ordering match the Accellera ordering, at a certain point that's no longer practical or desirable. This change manually updates the reference output for the tests that haven't been excluded for other reasons which have this sort of ordering problem. They have been individually examined, and as best as I can tell changing the output this way does not mask any underlying error. One or two real problems were discovered in addition to the ordering issues, and those were fixed in earlier changes. Change-Id: I915269998de3f33d5ab5d1fd754a830fd620184d Reviewed-on: https://gem5-review.googlesource.com/c/14918 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-10systemc: Ignore process control functions on terminated processes.Gabe Black
These functions can descend to the children of a terminated process, but should have no effect on that process itself. Change-Id: I6e4bdec8c492dd03d05bc1397aa080e8a51397c1 Reviewed-on: https://gem5-review.googlesource.com/c/14917 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-10systemc: Update signals before initing processes.Gabe Black
We were supposed to do one update phase before adding all processes which didn't have dont_initialize() called to the run queue. We were doing that in the opposite order. Change-Id: I6dd4108040d455dc78029da029a2eb5e7af819cb Reviewed-on: https://gem5-review.googlesource.com/c/14915 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-08base, systemc: Fix clang compilationGiacomo Travaglini
This patch is fixing the following issues: - base: typename should be used only for types - systemc: 'GCC_VERSION' is not defined for clang Change-Id: I27c94445d65691a08a0a14a0ffe6b6942f6c455f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14976 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-07mem: Compile tracePacket only when TRACING_ON is definedGiacomo Travaglini
If TRACING_ON is not defined (e.g. when building gem5.fast), clang compilations will fail reporting an unused function. Change-Id: I959dba6e9fcf74b951e16365077939ae4d4ef924 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14975 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-12-07mem-cache: Workaround for setWhenReady assertionDaniel R. Carvalho
Change 174da8e2da6a896d2e97bc264f9c827a0f4c35ac added an assert that is not satisfiable with current implementation, breaking some regression tests. Change-Id: Ibafaf0c51906384364f0b2a4b931f8ec6126d858 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14955 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-12-06base: Ported circlebuf to CircularQueueRekai Gonzalez-Alberquilla
Ported the existing circlebuf on top of the CircularQueue to condense shared functionality and minimise code/functionality replication. Additional contributors: Gabor Dozsa. Change-Id: Ib4e67c638f0fb66b54cef77007a03439218bda7f Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13128 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-12-06base: Iterable CircularQueue implementationRekai Gonzalez-Alberquilla
The former implementation of CircleBuf is functional but a bit too tailored to match a use-case. This patches introduces a new iterable circular queue, which adds some more functionality so it can also be used for the newer LSQ implementation, where iteration and iterators are a very desirable feature. Additional contributors: Gabor Dozsa. Change-Id: I5cfb95c8abc1f5e566a114acdbf23fc52a38ce5e Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13127 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-12-05arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.ccTony Gutierrez
Change a66d12c guards the selection of getdents() in x86's process.cc file with SYS_getdents, however process.cc does not include the right header for SYS_getdents, which leads to x86 choosing the unimplemented call. This change adds sys/syscall.h to address the problem. This change also adds sys/syscall.hh to syscall_emu.cc, which only includes syscall.hh and may not be supported on all systems. Change-Id: If1adcf41e9e455de5f2827ba98c542fdcacdc22e Reviewed-on: https://gem5-review.googlesource.com/c/14775 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-12-05mem-cache: Remove writebacks parameter from serviceMSHRTargetsDaniel R. Carvalho
Change 8ba77ae8fc98a355082da2bd9fdc6ecf4928f725 introduced the writebacks parameter, but it was never used. Change-Id: I225e5b399de42d77c72fc0012d3dc93ef39b8853 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14896 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-12-04mem-cache: Add getter and setter to CacheBlk::whenReadyDaniel R. Carvalho
Add a getter and a setter function to access CacheBlk::whenReady to encapsulate the variable and allow error checking. This error checking consists on verifying that writes to a block after it has been inserted follow a chronological order. As a side effect, tickInserted retain its value until updated, that is, it is not reset in invalidate(). Change-Id: Idc3c5a99c3f002ee9acc2424f00e554877fd3a69 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14715 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-12-04base: Fix fiber compilation issue for Mac OSNikos Nikoleris
Mac OS has deprecated the use of ucontext and at the moment we are using a workaround to enable it. A side-effect is that the code is marked as _POSIX_C_SOURCE and consequently <sys/mman.h> requires the code to be also marked as _DARWIN_C_SOURCE to include the definition of MAP_ANONYMOUS. Change-Id: I65550d11a0a21cd36d832a7de6320e7e3f332a9d Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14817 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-04base, sim: Add missing destructorsNikos Nikoleris
Derived classes with virtual functions need to define a virtual destructor or a protected destructor otherwise calling the base class destructor has undefined behavior. This change adds a virtual distructor in the base class. Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14815 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-12-03base: Add type alias for raw pointer in RefCountingPtrGiacomo Gabrielli
Change-Id: Ied2204566a8fc5c34fb4702301051b8e5ab84ffe Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13717 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-12-03mem-cache: Optimize sector valid and secure checkDaniel R. Carvalho
Previously a loop was being done to check whether the block was valid/secure or not. Variables have been added to skip this loop and save and update sector block state when sub-blocks are validated, invalidated and secured. Change-Id: Ie1734f7dfda9698c7bf22a1fcbfc47ffb9239cea Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14363 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-12-03cpu: Change raw pointers to STL ContainersRekai Gonzalez-Alberquilla
This patch changes two members from being raw pointers to being STL containers. The reason behind, other than cleanlyness and arguable OO best practices is that containers have more intronspections capabilities than naked pointers do, as the size is known. Using STL containers adds little overhead and eases the automation of process during debugging (gdb). Change-Id: I4d9d3eedafa8b5e50ac512ea93b458a4200229f2 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13126 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-12-03arch-arm: correctly set floats from GDB on aarch64Ciro Santilli
aarch64 floating point registers are now stored as vector type, but this was not updated in the stub. Change-Id: I4a2bc1cea0eec9beeb5bbd49e2a868b9d5ed0a42 Reviewed-on: https://gem5-review.googlesource.com/c/14498 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-14 00:42:58 +0000