summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2011-08-19ARM: Fix a memory leak with the table walker.Ali Saidi
2011-08-19Prefetcher: Fix some memory leaks with the prefetcher.Ali Saidi
2011-08-19ARM: quiet what can be a very noise CLCD controller.Ali Saidi
2011-08-16InOrder: Make cache_unit.hh include hashmap.hh explicitly, not transitively.Gabe Black
2011-08-16O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.Gabe Black
2011-08-15Ruby: Initialize some variables.Nilay Vaish
2011-08-14O3: When squashing, restore the macroop that should be used for fetching.Gabe Black
2011-08-14O3: Add a pointer to the macroop for a microop in the dyninst.Gabe Black
2011-08-13X86: Use IsSquashAfter if an instruction could affect fetch translation.Gabe Black
2011-08-13O3: At the end of an instruction, force fetchAddr to something sensible.Gabe Black
2011-08-09O3: Stop using the current macroop no matter why you're leaving it.Gabe Black
2011-08-09O3: When waiting to handle an interrupt, let everything drain out.Gabe Black
2011-08-08BuildEnv: Eliminate RUBY as build environment variableNilay Vaish
2011-08-07O3: Get rid of the unused addToRemoveList function.Gabe Black
2011-08-07O3: Let squashed and deferred instructions issue.Gabe Black
2011-08-07O3: Fix uninitialized variable in the tournament branch predictor.Ali Saidi
2011-08-07Translation: Use a pointer type as the template argument.Gabe Black
2011-08-03Ruby: Remove files and includes not in useNilay Vaish
2011-08-02O3: Get rid of the raw ExtMachInst constructor on DynInsts.Gabe Black
2011-08-02Scons: Make some Action objects fit the abreviated output format.Gabe Black
2011-08-02Scons: Drop RUBY as compile time option.Nilay Vaish
2011-07-31O3: Implement memory mapped IPRs for O3.Gabe Black
2011-07-30O3: Fix corner case squashing into the microcode ROM.Gabe Black
2011-07-27SLICC: Put functions of a controller in its .cc fileNilay Vaish
2011-07-15Mem: Fix issue with prefetches originating at non-L1 caches getting stale dataAli Saidi
2011-07-15O3: Create a pipeline activity viewer for the O3 CPU model.Giacomo Gabrielli
2011-07-15ARM: Fix SWP/SWPB undefined instruction behaviorWade Walker
2011-07-15ARM: Add two unimplemented miscellaneous registers.Wade Walker
2011-07-11X86: implements copyRegs() functionNilay Vaish
2011-07-11ISA: Get rid of the unused mem_acc_type template parameter.Gabe Black
2011-07-10Branch predictor: Fixes the tournament branch predictor.Mrinmoy Ghosh
2011-07-10O3: Fix up pipelining icache accesses in fetch stage to function properlyGeoffrey Blake
2011-07-10IO: Handle case where ISA Fake device is being used as a fake memory.Ali Saidi
2011-07-10O3: Make sure fetch doesn't go off into the weeds during speculation.Ali Saidi
2011-07-10Config: Add support for a Self.all proxy objectAli Saidi
2011-07-10ARM: Fix mp interrupt bug in GIC.Daniel Johnson
2011-07-07alpha:hwrei:rollback for o3Korey Sewell
2011-07-06ruby: added generic dma machineBrad Beckmann
2011-07-06MOESI_hammer: Fixed uniprocessor DMA bugBrad Beckmann
2011-07-05slicc: add a protocol statement and an include statementNathan Binkert
2011-07-05slicc: cleanup slicc code and make it less verboseNathan Binkert
2011-07-05grammar: better encapsulation of a grammar and parsingNathan Binkert
2011-07-05ISAs: Streamline some spots where Mem is used in the ISA descriptions.Gabe Black
2011-07-05ISA parser: Define operand types with a ctype directly.Gabe Black
2011-07-05ISA parser: Simplify operand type handling.Gabe Black
2011-07-03Merged with Gabe's recent changes.Nilay Vaish
2011-07-03Network_test: Conform it with functional access changes in RubyNilay Vaish
2011-07-02ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.Gabe Black
2011-07-02ExecContext: Get rid of the now unused read/write templated functions.Gabe Black
2011-07-02ISA: Use readBytes/writeBytes for all instruction level memory operations.Gabe Black