gem5 - gem5

Age	Commit message (Collapse)	Author
2009-05-20	igbe: Fix descriptor cache bug.	Steve Reinhardt

2009-05-17	includes: sort includes again	Nathan Binkert

2009-05-17	includes: use base/types.hh not inttypes.h or stdint.h	Nathan Binkert

2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
	--HG-- rename : src/sim/host.hh => src/base/types.hh
2009-05-13	stats: tidy up the Distribution type a little bit	Nathan Binkert

2009-05-13	stats: fancy is a bad name	Nathan Binkert

2009-05-13	stats: clean up the code for printing stats	Nathan Binkert

2009-05-13	mips-merge: merge hello world regress for inorder cpu	Korey Sewell
	w/latest changes
2009-05-12	ruby: deal with printf warnings and convert some to cprintf	Nathan Binkert

2009-05-12	ruby: remove random uint typedef and use unsigned	Nathan Binkert

2009-05-12	ruby: Make ruby's Map use hashmap.hh to simplify things.	Nathan Binkert

2009-05-12	gcc: work around a bogus gcc error	Nathan Binkert

2009-05-12	slicc: work around improper initialization of a global in slicc.	Nathan Binkert

2009-05-12	slicc: clean up the slicc environment so things build properly on mac.	Nathan Binkert

2009-05-13	inorder-mips: Remove eaComp & memAcc; use 'visible' eaComp	Korey Sewell
	Inorder expects eaComp to be visible through StaticInst object. This mirrors a similar change to ALPHA... Needs to be done for SPARC and whatever other ISAs want to use InOrderCPU
2009-05-13	arch-mips: add regWidth constant to float regfile	Korey Sewell

2009-05-12	cpus: add InOrderCPU to default build	Korey Sewell
	regressions need this so they build the model
2009-05-12	alpha-isa: add mt.hh so it can compile with inorder	Korey Sewell

2009-05-12	inorder-resources: delete events	Korey Sewell
	make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor
2009-05-12	inorder-tlb-cunit: merge the TLB as implicit to any memory access	Korey Sewell
	TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * *
2009-05-12	inorder-tlb: squash insts in TLB correctly	Korey Sewell
	TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly * * *
2009-05-12	inorder-faults: ignore unalign translation faults for prefetches	Korey Sewell

2009-05-12	inorder-stc: update interface to handle store conditionals	Korey Sewell

2009-05-12	inorder-float: Fix storage of FP results	Korey Sewell
	inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from the actual floating point register file, the model can figure out what it needs to store
2009-05-12	inorder-fetch: update model to use predecoder	Korey Sewell

2009-05-12	inorder-mem: clean up allocation/deletion of requests/packets	Korey Sewell
	* * *
2009-05-12	inorder-mem: skeleton support for prefetch/writehints	Korey Sewell

2009-05-12	inorder-o3: allow both to compile together	Korey Sewell
	allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
2009-05-12	inorder-unified-tlb: use unified TLB instead of old TLB model	Korey Sewell

2009-05-12	inorder-miscregs: Fix indexing for misc. reg operands and update ↵	Korey Sewell
	result-types for better tracing of these types of values
2009-05-12	inorder/alpha-isa: create eaComp object visible to StaticInst through ISA	Korey Sewell
	Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * *
2009-05-12	inorder-bpred: edits to handle non-delay-slot ISAs	Korey Sewell
	Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
2009-05-12	inorder-alpha-port: initial inorder support of ALPHA	Korey Sewell
	Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.)
2009-05-12	isa-parser: made a few changes, but not author-worthy	Korey Sewell

2009-05-11	ruby: assert(false) should be panic.	Nathan Binkert
	This also fixes some compiler warnings
2009-05-11	stats: remove a few compat leftovers	Nathan Binkert

2009-05-11	python: pull out common code from main that processes arguments	Nathan Binkert

2009-05-11	stats: forgot an include for the mysql stuff	Nathan Binkert

2009-05-11	scons: add include guards to info.hh	Nathan Binkert

2009-05-11	ruby: add RUBY sticky option that must be set to add ruby to the build	Nathan Binkert
	Default is false
2009-05-11	ruby: Working M5 interface and updated Ruby interface.	Daniel Sanchez
	This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu> RubyMemory is now both a driver for Ruby and a port for M5. Changed makeRequest/hitCallback interface. Brought packets (superficially) into the sequencer. Modified tester infrastructure to be packet based. and Ruby can be used together through the example ruby_se.py script. SPARC parallel applications work, and the timing seems right from combined M5/Ruby debug traces. To run, % build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
2009-05-11	ruby: Check stderr and not stdin before hanging on an assert.	Steve Reinhardt

2009-05-11	ruby: decommission code	Polina Dudnik
	1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.* 2. Decomissioned all bloom filters 3. Decomissioned ruby/simics directory
2009-05-11	ruby: removed dead functions from the sequencer	Derek Hower

2009-05-11	ruby: Removed g_SIMULATING flag	Polina Dudnik
	1. removed checks from tester files 2. removed else clause in Sequencer and DirectoryMemory else clause is needed by the tester, it is up to Derek to revive it elsewhere when he gets to it Also: 1. Changed m_entries in DirectoryMemory to a map 2. And replaced SIMICS_read_physical_memory with a call to now-dummy Derek's-to-be readPhysMem function
2009-05-11	ruby: Remove transactional access types (e.g. LD_XACT) from CacheRequestType	Polina Dudnik
	1. Modified enumeration 2. Also modified profiler 3. Remove transactions from Tester 4. Edited XACT_MEM out of Synthetic Driver
2009-05-11	ruby: reordered Debug and RubyConfig::init to fix segfault	Polina Dudnik
	due to uninitialized output file pointer.
2009-05-11	ruby: Disabled RubyEventQueue's deletion of its home-grown priority heap.	Dan Gibson
	Temporarily to fix unusual memory problem.
2009-05-11	ruby: Migrate all of ruby and slicc to SCons.	Nathan Binkert
	Add the PROTOCOL sticky option sets the coherence protocol that slicc will parse and therefore ruby will use. This whole process was made difficult by the fact that the set of files that are output by slicc are not easily known ahead of time. The easiest thing wound up being to write a parser for slicc that would tell me. Incidentally this means we now have a slicc grammar written in python.
2009-05-11	ruby: clean up a few warnings	Nathan Binkert