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AgeCommit message (Expand)Author
2011-06-19cpus/isa: add a != operator for pcstateKorey Sewell
2011-06-19inorder: update bpred codeKorey Sewell
2011-06-19inorder: add types for dependency checksKorey Sewell
2011-06-19inorder: use flattenIdx for reg indexingKorey Sewell
2011-06-19simple-thread: give a name() function for debugging w/the SimpleThread objectKorey Sewell
2011-06-19inorder: use m5_hash_map for skedCacheKorey Sewell
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-06-16ARM: Handle case where new TLB size is different from previous TLB size.Ali Saidi
2011-06-16ARM: Fix memset on TLB flush and initializationChander Sudanthi
2011-06-14Ruby: Correct set LONG_BITS and INDEX_SHIFT in class Set.Nilay Vaish
2011-06-12Loader: Handle bad section names when loading an ELF file.Gabe Black
2011-06-10o3: missing newlines on some dprintfsKorey Sewell
2011-06-10sparc: don't use directcntrl branch flagKorey Sewell
2011-06-09sparc: compilation fixes for inorderKorey Sewell
2011-06-08Ruby: Correctly set access permissions for directory entriesNilay Vaish
2011-06-08Mem: Use sysconf to get the page size instead of the PAGE_SIZE macro.Gabe Black
2011-06-07ISA parser: Loosen the regular expressions matching filenames.Gabe Black
2011-06-07gcc 4.0: Add some virtual destructors to make gcc 4.0 happy.Gabe Black
2011-06-03SLICC: Remove machine name as prefix to functionsNilay Vaish
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-06-02scons: rename some things from m5 to gem5Nathan Binkert
2011-06-02copyright: Add code for finding all copyright blocks and create a COPYING fileNathan Binkert
2011-06-02copyright: clean up copyright blocksNathan Binkert
2011-06-01SimObject: allow modules in subclass definitionsSteve Reinhardt
2011-05-31orion: bug fix in link power, and some reorgTushar Krishna
2011-05-31garnet: added network ptr to links to be used by orionTushar Krishna
2011-05-29Misc: Remove the URL from warnings, fatals, panics, etc.Gabe Black
2011-05-25Name: Replace M5 with gem5 in a few places it's printed on startup.Gabe Black
2011-05-23sim: style fixes in sim/process.hhSteve Reinhardt
2011-05-23syscall emul: fix Power Linux mmap constant, plus other cleanupSteve Reinhardt
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt
2011-05-23config: tweak ruby configs to clean up hierarchySteve Reinhardt
2011-05-23config: reinstate implicit parenting on parameter assignmentSteve Reinhardt
2011-05-23sim: add some DPRINTFs for debugging unserializationSteve Reinhardt
2011-05-23O3: Fix offset calculation into storeQueue buffer for store->load forwardingGeoffrey Blake
2011-05-23O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.Geoffrey Blake
2011-05-23O3: Fix issue with interrupts/faults occuring in the middle of a macro-opGeoffrey Blake
2011-05-21garnet: use vnet_type from protocol to decide buffer depthsTushar Krishna
2011-05-20slicc: added vnet_type to MI_exampleTushar Krishna
2011-05-18gcc: fix an uninitialized variable warning from G++ 4.5Nathan Binkert
2011-05-18slicc: added vnet_type field to identify response vnets from othersTushar Krishna
2011-05-18garnet: rename and rearrange config parameters.Tushar Krishna
2011-05-13ARM: Generate condition code setting code based on which codes are set.Ali Saidi
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-13Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.Chander Sudanthi
2011-05-13ARM: Better RealView/Versatile EB platform support.Chander Sudanthi
2011-05-13O3: Fix an issue with a load & branch instruction and mem dep squashingGeoffrey Blake