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AgeCommit message (Expand)Author
2011-03-26mips: cleanup ISA-specific codeKorey Sewell
2011-03-25Arm: Add in a missing miscRegName.Gabe Black
2011-03-24Arm: Get rid of unused and incomplete setCp15Register and readCp15Register.Gabe Black
2011-03-24Arm: Get rid of the unused copyStringArray32 method from Arm process classes.Gabe Black
2011-03-24ISA parser: Set up op_src_decl and op_dest_decl for pc operands.Gabe Black
2011-03-22This patch fixes a build error in networktest.cc that occurs with gcc4.2Tushar Krishna
2011-03-22Ruby: Remove CacheMsg class from SLICCNilay Vaish
2011-03-21This patch makes garnet use the info about active and inactive vnets during a...Tushar Krishna
2011-03-21fix garnet fleible pipelineTushar Krishna
2011-03-21This patch adds the network tester for simple and garnet networks.Tushar Krishna
2011-03-20SLICC: Remove WakeUp* import calls from ast/__init__.pyNilay Vaish
2011-03-19Ruby: Convert CacheRequestType to RubyRequestTypeNilay Vaish
2011-03-19Ruby: Convert AccessModeType to RubyAccessModeNilay Vaish
2011-03-19MOESI_hammer: minor fixes to full-bit dirBrad Beckmann
2011-03-19Ruby: dma retry fixBrad Beckmann
2011-03-19RubyPort: minor fixes to trace flag and dprintfsBrad Beckmann
2011-03-19ruby: added useful dma progress dprintfBrad Beckmann
2011-03-19slicc: improved invalid transition messageBrad Beckmann
2011-03-19MOESI_hammer: fixed dma bug with shared dataBrad Beckmann
2011-03-19MOESI_CMP_directory: significant dma bug fixesBrad Beckmann
2011-03-18SLICC: Remove external_type for structuresNilay Vaish
2011-03-18SLICC: Remove the keyword wake_up_dependentsNilay Vaish
2011-03-18SLICC: Remove the keyword wake_up_all_dependentsNilay Vaish
2011-03-18swig: get rid of m5.internal.random module (swig/random.i)Steve Reinhardt
2011-03-18base: disable FastAlloc in debug builds by defaultSteve Reinhardt
2011-03-17Automated merge with ssh://hg@repo.m5sim.org/m5Ali Saidi
2011-03-17ARM: Add minimal ARM_SE support for m5threads.Chris Emmons
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
2011-03-17ARM: Implement the Instruction Set Attribute Registers (ISAR).Ali Saidi
2011-03-17ARM: Identify branches as conditional or unconditional and direct or indirect.Ali Saidi
2011-03-17ARM: Fix small bug with VLDM/VSTM instructions.Ali Saidi
2011-03-17ARM: Detect and skip udelay() functions in linux kernel.Ali Saidi
2011-03-17ARM: Allow conditional quiesce instructions.Ali Saidi
2011-03-17ARM: Fix RFE macrop.Matt Horsnell
2011-03-17ARM: Rename registers used as temporary state by microops.Matt Horsnell
2011-03-17O3: Send instruction back to fetch on squash to seed predecoder correctly.Ali Saidi
2011-03-17O3: Cleanup the commitInfo comm struct.Ali Saidi
2011-03-17ARM: Previous change didn't end up setting instFlags, this does.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-03-17O3: Fix unaligned stores when cache blockedAli Saidi
2011-03-17Ruby: minor bugfix, line did not adhere to some macro usage conventions.Lisa Hsu
2011-03-17Ruby: expose a simple mod function in slicc interface.Lisa Hsu
2011-03-11SCons: Stop embedding the mercurial revision into the binary.Gabe Black
2011-03-11Gems: Eliminate the now unused GEMS_ROOT scons variable.Gabe Black
2011-03-11Ruby: Get rid of the dead ruby tester.Gabe Black
2011-03-08Alpha: Fix the datatypes of some values read from the simulated kernel.Yi Xiang
2011-03-03SCons: Clean up some inconsistent capitalization in scons options.Gabe Black
2011-03-02X86: Use the npc as the pc when doing a nativetrace, not what M5 considers th...Gabe Black
2011-03-02X86: Decode the mysterious and elusive ffreep x87 instruction.Gabe Black
2011-03-01Spelling: Fix the a spelling error by changing mmaped to mmapped.Gabe Black
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