gem5 - gem5

Age	Commit message (Expand)	Author
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-03-22	Scons: Remove Werror=False in SConscript files	Andreas Hansson
2012-03-21	Python: Fix a conditional expression that requires Python 2.5	Andreas Hansson
2012-03-21	ARM: Fix case where cond/uncond control is mis-specified	Nathanael Premillieu
2012-03-21	ARM: Clean up condCodes in IT blocks.	Ali Saidi
2012-03-21	ARM: IT doesn't need to be serializing.	Geoffrey Blake
2012-03-21	O3: Fix sizing of decode to rename skid buffer.	Andrew Lukefahr
2012-03-21	ARM: Add RTC to PBX System	Koan-Sin Tan
2012-03-21	O3: Fix size of skid buffer between fetch and decode when widths are different	Brian Grayson
2012-03-21	ARM: Fix uninitialized value in ARM RTC model.	Ali Saidi
2012-03-19	Garnet: Stats at vnet granularity + code cleanup	Tushar Krishna
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2012-03-19	clang: Fix recently introduced clang compilation errors	Andreas Hansson
2012-03-19	scripts: Fix to ensure that port connection count is always set	Andreas Hansson
2012-03-11	O3: Add fatal when fetchWidth > Impl::MaxWidth.	Brian Grayson
2012-03-09	ARM: Fix branch prediction issue with CB(N)Z instruction	Brian Grayson
2012-03-09	O3/Ozone: Eliminate dead code counting software prefetch insts	Geoffrey Blake
2012-03-09	CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU	Geoffrey Blake
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-09	ARM: Don't reset CPUs that are going to be switched in.	Ali Saidi
2012-03-09	System: Move code in initState() back into constructor whenever possible.	Ali Saidi
2012-03-09	ARM: Fix valgrind reported error on O3 that was causing minor stats changes.	Ali Saidi
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-06	build scripts: Made minor modifications to reduce build overhead time.	Marc Orr
2012-03-02	DynInst: get rid of dead MyHash code.	Steve Reinhardt
2012-03-02	CPU: Check that the interrupt controller is created when needed	Andreas Hansson
2012-03-02	Ruby: Rename RubyPort::sendTiming to avoid overriding base class	Andreas Hansson
2012-03-02	ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.	Ali Saidi
2012-03-01	ARM: FIx missing cf controller connection.	Ali Saidi
2012-03-01	VNC: spacing	Chander Sudanthi
2012-03-01	ARM: Add support for Versatile Express extended memory map	Ali Saidi
2012-03-01	ARM: Add RTC device for ARM platforms.	Ali Saidi
2012-03-01	ARM: Add limited CP14 support.	Matt Horsnell
2012-03-01	Cache: Fix an issue with LRU when bonus block is used to complete transaction.	Ali Saidi
2012-03-01	ARM: move kernel func event to correct location.	Dam Sunwoo
2012-03-01	ARM: fix bits-to-fp conversion function declarations.	Giacomo Gabrielli
2012-03-01	x86: Fix x86 TLB and Walker	Nilay Vaish
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-02-29	MEM: Make all the port proxy members const	Andreas Hansson
2012-02-29	SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1	Andreas Hansson
2012-02-26	X86: Use the M5PanicFault fault in execute methods instead of calling panic.	Gabe Black
2012-02-24	MEM: Simplify cache ports preparing for master/slave split	Andreas Hansson
2012-02-24	MEM: Prepare mport for master/slave split	Andreas Hansson
2012-02-24	Ruby: Simplify tester ports by not using SimpleTimingPort	Andreas Hansson
2012-02-24	MEM: Move all read/write blob functions from Port to PortProxy	Andreas Hansson
2012-02-24	MEM: Make port proxies use references rather than pointers	Andreas Hansson
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-02-24	MEM: Fatal when no port can be found for an address	Andreas Hansson
2012-02-20	SimObject: make get_config_as_dict() tolerate undefined params	Steve Reinhardt