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AgeCommit message (Expand)Author
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
2011-01-03RefCount: Fix reference counting pointer == and != with a T* on the left.Gabe Black
2010-12-30swig: use <> for system %includes instead of ""Nathan Binkert
2010-12-23PerfectCacheMemory: Add return statements to two functions.Nilay Vaish
2010-12-22This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh f...Nilay Vaish
2010-12-21memtest: delete some crufty dead codeSteve Reinhardt
2010-12-21Get rid of unused file src/base/dbl_list.hhSteve Reinhardt
2010-12-21stats: allow stats to be reset even if no objects have been instantiatedNathan Binkert
2010-12-21importer: fix error messageNathan Binkert
2010-12-21scons: remove extra dependenciesNathan Binkert
2010-12-20Style: Replace some tabs with spaces.Gabe Black
2010-12-20Params: Fix a broken error message in verifyIp.Gabe Black
2010-12-09ARM: Take advantage of new PCState syntax.Gabe Black
2010-12-09ARM: Get rid of some unused FP operands.Gabe Black
2010-12-08Merge.Gabe Black
2010-12-08ruby: remove Ruby asserts for m5.fastBrad Beckmann
2010-12-08Alpha: Take advantage of new PCState syntax.Gabe Black
2010-12-08MIPS: Take advantage of new PCState syntax.Gabe Black
2010-12-08POWER: Take advantage of new PCState syntax.Gabe Black
2010-12-08SPARC: Take advantage of new PCState syntax.Gabe Black
2010-12-08X86: Take advantage of new PCState syntax.Gabe Black
2010-12-07ISA: Get the parser to support pc state components more elegantly.Gabe Black
2010-12-07O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).Ali Saidi
2010-12-07O3: Support squashing all state after special instructionAli Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-12-07ARM: Support switchover with hardware table walkersAli Saidi
2010-12-01ruby: Converted old ruby debug calls to M5 debug callsNilay Vaish
2010-11-26IGbE: return 0 on an invalid descriptor size instead of -1.Ali Saidi
2010-11-23Copyright: Add AMD copyright to the param changes I just made.Gabe Black
2010-11-23Params: Add parameter types for IP addresses in various forms.Gabe Black
2010-11-23X86: Loosen an assert for x86 and connect the APIC ports when caches are used.Gabe Black
2010-11-23X86: Obey the PCD (cache disable) bit in the page tables.Gabe Black
2010-11-22X86: Mark IO space accesses as uncachable.Gabe Black
2010-11-22IDE,X86: Fix IDE controller BAR configuration for x86.Gabe Black
2010-11-20random: small comment about our random number generator and its originNathan Binkert
2010-11-19SE: Fix simulating more than 4GB of RAM in SE modeAli Saidi
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-18O3: Fix fp destination register flattening, and index offset adjusting.Gabe Black
2010-11-15O3: Make O3 support variably lengthed instructions.Gabe Black
2010-11-15O3: reset architetural state by calling clear()Ali Saidi
2010-11-15ARM: Add comment about the organization of the IT state registerAli Saidi
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15O3: prevent a squash when completeAcc() modifies misc reg through TC.Min Kyu Jeong
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi
2010-11-15SCons: Cleanup SCons output during compileAli Saidi
2010-11-15ARM: Add a Keyboard Mouse Interface controllerWilliam Wang
2010-11-15ARM: Implement a CLCD Frame bufferWilliam Wang
2010-11-15ARM: Add support for GDB on ARMWilliam Wang
2010-11-15ARM: Make utility.hh meet style guidelinesAli Saidi