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2016-07-19dev, dist: Fixed a scheduling bug in the etherswitchMohammad Alian
This patch fixes a bug in etherswitch. When a packet gets inserted in the output fifo, the txEvent has to always be reschedule, not only when an event is already scheduled. This can raise the assertion in the reschedule function.
2016-07-11base: Fix inverted check in ELF .text size warningAndreas Sandberg
2016-07-11arm: Don't consult the TLB test iface for functional translationsAndreas Sandberg
Don't consult the TLB test interface for PA's returned by functional translations by the AT instruction. We implement this by chaning the ISA code to synthesize 0-length functional reads for the TLB lookup. The TLB then bypasses the final PA check in the tester if the size is zero. Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-07-11base: Convert ELF .text size check assertion to a warningAndreas Sandberg
The ELF loader currently has an assertion that checks if the size of a loaded .text secion is non-zero. This is useful in the general case as an empty text section normally indicates that there is something strange with the ELF file. However, asserting isn't very useful. This changeset converts the assert into a warning that tells the user that something strange is happening. Change-Id: I313e17847b50a0eca00f6bd00a54c610d626c0f0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-07-11mem: Remove stale argument from a DPRINTF in the cache codeNikos Nikoleris
Change-Id: I70dd11c23b45dfc606ef08233d2e50fcc0817505 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-07-01ruby: Fix double statistic registration in garnetMatthew Poremba
Currently garnet will not run due to double statistic registration of new stats in ClockedObject. This occurs because a temporary array named 'cls' is being added as a child to garnet internal and external link SimObjects. This patch simply renames the temporary array which prevents it from being added as a child object and avoids the assertion that a statistic was already registered. Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01ext: Update DRAMPowerMatthias Jung
Sync DRAMPower to external tool This patch syncs the DRAMPower library of gem5 to the external one on github (https://github.com/ravenrd/DRAMPower) of which I am a maintainer. The version used is the commit: 902a00a1797c48a9df97ec88868f20e847680ae6 from 07. May. 2016. Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01mem: different HMC configurationAbdul Mutaal Ahmad
In this new hmc configuration we have used the existing components in gem5 mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different architecture for HMC. Highlights 1- It explores 3 different HMC architectures 2- It creates 4-HMC crossbars and attaches 16 vault controllers with it. This will connect vaults to serial links 3- From the previous version, HMCController with round robin funtionality is being removed and all the serial links are being accessible directly from user ports 4- Latency incorporated by HMCController (in previous version) is being added to SerialLink Committed by Jason Lowe-Power <jason@lowepower.com>
2016-06-28scons: Track swig packages when loading embedded swig codeAndreas Hansson
This patch changes how the embedded swig code is loaded to ensure that gem5 works with swig 3.0.9. For Python 2.7 and above, swig 3.0.9 now relies on importlib, and actually looks in the appropriate packages, even for the wrapped C code. However, the swig wrapper does not explicitly place the module in the right package (it just calls Py_InitModule), and we have to take explicit action to ensure that the swig code can be loaded. This patch adds the information to the generated wrappers and the appropriate calls to set the context as part of the swig initialisation. Previous versions of swig used to fall back on looking in the global namespace for the wrappers (and still do for Python 2.6), but technically things should not work without the functionality in this patch.
2016-06-20arm: Mark uninitialized new TLB entries as not validNikos Nikoleris
Previously when we initialized the TLB we would allocate a number of TLB entries which would be marked as valid. As a result the TLB contained an entry which would be considered a valid entry for the 0 page. Change-Id: I23ace86426a171a4f6200ebeb29ad57c21647036 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20sim: Added library include to fix build errors on clang-703.0.31Reiley Jeapaul
The use of array tuples, requires an explicit include of the array library Change-Id: I06730051777a97edf80e41a5604184b387b12239 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20mem: Fix the snoop filter when there is a downstream addr mapperNikos Nikoleris
The snoop filter handles requests in two steps which preceed and follow the call to send the packet downstream. An address mapper could possibly change the address of the packet when it is sent downstream breaking the snoop filter assumption that the address is unchanged Change-Id: Ib2db755e9ebef4f2f7c0169a46b1b11185ffbe79 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20mem: Resolve TrafficGen trace relative to the configAndreas Sandberg
The traffic generator currently resolves relative trace paths relative to gem5's current working directory. This can lead to surprising results for relative paths where the expectation would normally be that they are resolved relative to the configuration file. This changeset implements config-relative trace file lookups. The old behavior is kept as a fallback for configs that expect that behavior. Change-Id: I1bda4e16725842666ffc37dcb6838c23a6ff138c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-06-20kern, arm: Dump dmesg on kernel panic/oopsAndreas Sandberg
Add helper functions to dump the guest kernel's dmesg buffer to a text file in m5out. This functionality is split into two parts. First, a dmesg dump function that can be used in other places: void Linux::dumpDmesg(ThreadContext *, std::ostream &) This function is used to implement two PCEvents: DmesgDumpEvent and KernelPanic event. The only difference between the two is that the latter produces a gem5 panic instead of a warning in addition to dumping the kernel log. Change-Id: I6d2af1d666ace57124089648ea906f6c787ac63c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-06-20base: Fix multiple names to one address bug in SymbolTableAndreas Sandberg
The SymbolTable class currently assumes that at most one symbol can point to a given address. If multiple symbols point to the same address, only the first one gets added to the internal symbol table since there is already a match in the address table. This changeset converts the address table from a map into a multimap to be able to handle cases where an address maps to multiple symbols. Additionally, the insert method is changed to not fail if there is a match in the address table. Change-Id: I6b4f1d5560c21e49a4af33220efb2a8302961768 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-06-18gpu-compute: Fixed a bug in decoding Atomic STTuan Ta
There is a mismatch between DataType and SrcDataType in constructing Atomic ST instruction. The mismatch causes atomic_store and atomic_store_explicit function to store incorrect value in memory.
2016-06-09gpu-compute: parametrize Wavefront sizejkalamat
Eliminate the VSZ constant that defined the Wavefront size (in numbers of work items); replaced it with a parameter in the GPU.py configuration script. Changed all data structures dependent on the Wavefront size to be dynamically sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at initialization time.
2016-06-08dist, dev: Fixed the packet ordering in etherswitchMohammad Alian
This patch fixes the order that packets gets pushed into the output fifo of etherswitch. If two packets arrive at the same tick to the etherswitch, we sort and push them based on their source port id. In dist-gem5 simulations, if there is no ordering inforced while two packets arrive at the same tick, it can lead to non-deterministic simulations Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-06-07sim: Make clang happyAndreas Hansson
Once again appeasing clang.
2016-06-07sim: added missing include to mathexpr.hhSergei Trofimov
mathexpr.hh uses std::function<> but was not including the appropriate header, which resulted in an error build/ARM/sim/mathexpr.hh:51:18: error: 'function' in namespace 'std' does not name a template type typedef std::function<double(std::string)> EvalCallback; This commit adds the missing include. Change-Id: I6c01d77d4354c6de838538f137a38f75f9866166 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-06-06sim: Only print the power state transition warning onceAndreas Sandberg
A lot of objects seem to request no-op power transitions which currently results in large amounts of warnings. These warnings are benign and risk hiding more serious warnings. Make the warning a warn_once to prevent console flooding. Change-Id: I86c74b4224b167f14469250ef86ab69fde7a227e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-06pwr: Closing power and thermal feedback loopDavid Guillen Fandos
This patch makes thermal models use the power figures calculated by power models. Since there is a circular dependency between power and thermal (and thermal was pushed before) this patch closes that loop. Change-Id: I8bd5acf6a5026fdbbcfac47e33d27397f24a6f7d Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
2016-06-06sim: Adding support for power modelsDavid Guillen Fandos
This patch adds some basic support for power models in gem5. The power interface is defined so it can interact with thermal models as well. It implements a simple power evaluator that can be used for simple power models that express power in the form of a math expression. These expressions can use stats within the same SimObject (or down its hierarchy) and some magic variables such as "temp" for temperature. In future patches we will extend this functionality to allow slightly more complex expressions. The model allows it to be extended to use other kinds of models. Change-Id: I76752f9638b6815e229fd74cdcb7721a305cbc4b
2016-06-06pwr: Low-power idle power state for idle CPUsDavid Guillen Fandos
Add functionality to the BaseCPU that will put the entire CPU into a low-power idle state whenever all threads in it are idle. Change-Id: I984d1656eb0a4863c87ceacd773d2d10de5cfd2b
2016-06-06stats: Silence unused power statsAndreas Sandberg
The power stats are currently very noisy even if no power model has been loaded. Silence stats that are either zero or nan. Change-Id: I7d0220c2fcf01131084a219228f140cfaddaf95b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-06pwr: Add power states to ClockedObjectDavid Guillen Fandos
Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats. Change-Id: Id086090a2ed720c9fcb37812a3c98f0f724907c6
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
Fixing an issue with regStats not calling the parent class method for most SimObjects in Gem5. This causes issues if one adds new stats in the base class (since they are never initialized properly!). Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
We want to extend the stats of objects hierarchically and thus it is necessary to register the statistics of the base-class(es), as well. For now, these are empty, but generic stats will be added there. Patch originally provided by Akash Bagdia at ARM Ltd.
2016-06-03gpu-compute: Fixed a bug in global memory pipelineTuan Ta
Added a condition when inflightStores is incremented to prevent a deadlock caused by many memory fence requests generated by a CU
2016-06-03ruby: Implement SwapReq supportMarco Elver
This implements SwapReq for Ruby memory. A SwapReq should be treated like a write, except that the response packet contains the overwritten data. Note that, in particular, the conditional checking for isStore/isLoad needs to be reversed, as a SwapReq is both.
2016-06-02arm: refactor page table format determinationCurtis Dunham
In particular, when EL0 is in AArch32 but EL1 is AArch64, AArch64 memory translation must be used. This is essential for typical AArch64/32 interworking use cases.
2016-06-02arm: Rewrite ERET to behave according to the ARMv8 ARMAndreas Sandberg
The ERET instruction doesn't set PSTATE correctly in some cases (particularly when returning to aarch32 code). Among other things, this breaks EL0 thumb code when using a 64-bit kernel. This changeset updates the ERET implementation to match the ARM ARM. Change-Id: I408e7c69a23cce437859313dfe84e68744b07c98 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-06-02arm: Correctly check FP/SIMD access permission in aarch32Andreas Sandberg
The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1 and higher are all 32-bit. This breaks interprocessing since an aarch64 EL1 uses different enable/disable bits. This change updates the permission checks to according to what is prescribed by the ARM ARM. Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-05-31arm: Enable LPAE support by defaultAndreas Sandberg
LPAE has been tested with Linux 4.4 and seems to work just fine. Let's enable it by default. Change-Id: Id88c6e3c91ae9c353279d42f2aa1f8a78485bd32 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-05-31arm: Correctly check translation mode (aarch64/aarch32)Andreas Sandberg
According to the ARM ARM (see AArch32.TranslateAddress in the pseudocode library), the TLB should be operating in aarch64 mode if the EL0 is aarch32 and EL1 is aarch64. This is currently not the case in gem5, which breaks 64/32 interprocessing. Update the check to match the reference manual. Change-Id: I6f1444d57c0e2eb5f8880f513f33a9197b7cb2ce Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-30scons: Bump minimum gcc version to 4.8Andreas Hansson
After reaching consensus on the mailing list, this patch officially makes gcc 4.8 the minimum. A few checks in the SConstruct are cleaned up as a result. This patch also adds "-fno-omit-frame-pointer" when using ASAN (which is part of the gcc/clang recommended flags).
2016-05-27cpu: fix lastStopped unserialisationIlias Vougioukas
MinorCPU fix for corrupt numCycles when resuming from a previous simulation. --- src/cpu/minor/cpu.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
2016-05-27power: Allow voltage to be configured via cmd lineAkash Bagdia
--- src/python/m5/params.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
2016-05-27arm: Use the target EL state when determining fault formatAndreas Sandberg
We currently check the current state instead of the state of the target EL when determining how we report a fault. This breaks interprocessing since EL0 in aarch32 would report its fault status using the aarch32 registers even if EL1 is in aarch64. Fix this to report the fault using the format of the target EL. Change-Id: Ic080267ac210783d1e01c722a4ddaa687dce280e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
2016-05-26arm: Fix incorrect TLB permission check in aarch32Andreas Sandberg
The TLB currently assumes that the pxn bit in an LPAE page descriptor disables execution from unprivileged mode. However, according to the architecture manual, this bit should disable execution from privileged modes. Update the TLB implementation to reflect this behavior. Change-Id: I7f1bb232d7a94a93fd601a9230223195ac952947 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-26arm: Make EL checks available in SE modeAndreas Sandberg
A lot of code assumes that it is possible to test what the highest EL is and if it is 64 bit. These calls currently don't work in SE mode since they rely on an instance of an ArmSystem. Change-Id: I0d1f261926a66ce3dc4fa116845ffb2a081446f2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-05-26mem: Fix memory leak in handling of deferred snoopsAndreas Hansson
This patch fixes a memory leak where deferred snoop packets never got deallocated. On the call to MSHR::handleSnoop these snoops were treated as if a response will be sent, as the MSHR was pendingModified. Consequently, a copy of the packet was created and added to the MSHR targets. However, an preceeding target to the same MSHR, originally from a CPU, was serviced before the snoop, and caused the block to be invalidated. This happens for ReadExReq and UpgradeReq. Note that the original snoop will receive a response, just not from the cache in question, but instead from the cache upstream that issued the ReadExReq or UpgradeReq. Change-Id: I4ac012fbc8a46cf693ca390fe9476105d444e6f4 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-26dev, arm: Add a flag to enable/disable gem5 GIC extensionsAndreas Sandberg
Make it possible to disable gem5 gic extensions by setting the gem5_extensions param to False from Python. Change-Id: Icb255105925ef49891d69cc9fe5cc55578ca066d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Geoffrey Blake <geoffrey.blake@arm.com>
2016-05-26cpu: Add a basic progress check to the TrafficGenAndreas Hansson
This patch adds a progress check to the TrafficGen so that it is easier to detect deadlock scenarios where the generator gets stuck waiting for a retry, and makes no further progress. Change-Id: Ifb8779ad0939f52c0518d0e867bac73f99b82e2b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
2016-05-26mem: Do not set cacheResponding on MSHR snoop if not respondingAndreas Hansson
This patch changes the flow control for HSHR::handleSnoop to ensure that we only set cacheResponding on the snoop packet if we are actually responding. This avoids situations where a responder is stalling indefinitely on a response that never arrives. Change-Id: I691dd01755b614b30203581aa74fc743b350eacc Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-26mem: Fix MemChecker unique_ptr type mismatchAndreas Hansson
This patch fixes the type of the unique_ptr instances, to ensure that the data that is allocated with new[] is also deleted with delete[]. The issue was highlighted by ASAN. Change-Id: I2c5510424959d862a9954d83e728d901bb18d309 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
2016-05-26arm: Fix heap overflow issue in Neon64Load operationAndreas Hansson
This patch fixes an issue identified by ASAN where the Neon64Load operation assumes the packet always contains 16 bytes. Change-Id: If24a7e461d60cb80970dfbe61d923d7d56926698 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-26arm, dev: Remove superfluous loop increment in flash deviceAndreas Hansson
As identified by clang-3.8, there was a superfluous loop increment in the flash device which is now removed. Change-Id: If46a1c4f72d3d4c9f219124030894ca433c790af Reviewed-by: Rene De Jong <rene.dejong@arm.com>
2016-05-26mem: fix headers include order in the cache related classesNikos Nikoleris
Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26mem: remove redudant check whether the cache forwards snoopsNikos Nikoleris
Change-Id: I57b56771086e1e2f512977fb7248d93c171ab925 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>