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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
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src
Age
Commit message (
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Author
2014-07-23
cpu: `Minor' in-order CPU model
Andrew Bardsley
2014-07-19
syscall emulation: fix fast build issue
Steve Reinhardt
2014-07-18
x86: make PioBus return BadAddress errors
Binh Pham
2014-07-18
sim: remove unused MemoryModeStrings array
Steve Reinhardt
2014-07-18
kern: get rid of unused linux syscall files
Steve Reinhardt
2014-07-18
syscall emulation: fix DPRINTF arg ordering bug
Steve Reinhardt
2014-07-09
base: fix operator== for comparing EthAddr objects
Anthony Gutierrez
2014-07-02
base: fix some bugs in EthAddr
Anthony Gutierrez
2014-07-01
util: Add DVFS perfLevel to checkpoint upgrade script
Radhika Jagtap
2014-06-30
power: Add basic DVFS support for gem5
Stephan Diestelhorst
2014-06-30
mem: DRAMPower trace output
Andreas Hansson
2014-06-30
mem: Add bank and rank indices as fields to the DRAM bank
Andreas Hansson
2014-06-30
mem: Extend DRAM row bits from 16 to 32 for larger densities
Andreas Hansson
2014-06-30
cpu: implement a bi-mode branch predictor
Anthony Gutierrez
2014-06-21
x86: fix table walker assertion
Binh Pham
2014-06-21
o3: make dispatch LSQ full check more selective
Binh Pham
2014-06-21
o3: split load & store queue full cases in rename
Binh Pham
2014-06-10
scons: Bump the compiler version to gcc 4.6 and clang 3.0
Andreas Hansson
2014-06-09
sim: More rigorous clocking comments
Joel Hestness
2014-05-31
style: eliminate equality tests with true and false
Steve Reinhardt
2014-05-23
ruby: slicc: remove unused ids DNUCA*
Nilay Vaish
2014-05-23
ruby: remove old protocol documentation
Nilay Vaish
2014-05-23
ruby: message buffer: drop dequeue_getDelayCycles()
Nilay Vaish
2014-05-23
cpu: o3: remove stat totalCommittedInsts
Nilay Vaish
2014-05-12
syscall emulation: clean up & comment SyscallReturn
Steve Reinhardt
2014-05-09
mem: Update DDR3 and DDR4 based on datasheets
Andreas Hansson
2014-05-09
mem: Add DRAM cycle time
Andreas Hansson
2014-05-09
mem: Simplify DRAM response scheduling
Andreas Hansson
2014-05-09
mem: Add precharge all (PREA) to the DRAM controller
Andreas Hansson
2014-05-09
mem: Remove printing of DRAM params
Andreas Hansson
2014-05-09
mem: Add tRTP to the DRAM controller
Andreas Hansson
2014-05-09
mem: Merge DRAM latency calculation and bank state update
Andreas Hansson
2014-05-09
mem: Add tWR to DRAM activate and precharge constraints
Andreas Hansson
2014-05-09
mem: Merge DRAM page-management calculations
Andreas Hansson
2014-05-09
mem: Add DRAM power states to the controller
Andreas Hansson
2014-05-09
mem: Ensure DRAM refresh respects timings
Andreas Hansson
2014-05-09
mem: Make DRAM read/write switching less conservative
Andreas Hansson
2014-04-17
arm: Make sure UndefinedInstructions are properly initialized
Ali Saidi
2014-04-17
arm: allow DC instructions by default so SE mode works
Ali Saidi
2014-04-17
sim, arm: implement more of the at variety syscalls
Ali Saidi
2014-05-09
cpu: Useful getters for ActivityRecorder
Andrew Bardsley
2014-05-09
cpu: Add flag name printing to StaticInst
Andrew Bardsley
2014-05-09
cpu: Timebuf const accessors
Andrew Bardsley
2014-05-09
arm: Add branch flags onto macroops
Andrew Bardsley
2014-05-09
cpu: Allow setWhen on trace objects
Andrew Bardsley
2014-05-09
arm: add preliminary ISA splits for ARM arch
Curtis Dunham
2014-05-09
arch: teach ISA parser how to split code across files
Curtis Dunham
2014-05-09
config: Avoid generating a reference to myself for Parent.any
Geoffrey Blake
2014-05-09
arch, arm: Preserve TLB bootUncacheability when switching CPUs
Geoffrey Blake
2014-05-09
cpu: add more instruction mix statistics
Curtis Dunham
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