| Age | Commit message (Expand) | Author |
|---|
| 2013-02-10 | ruby: enable multiple clock domains | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Cycles (final patch in the series) | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Cycles in garnet fixed and flexible | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Tick in replacement policy classes | Nilay Vaish |
| 2013-02-10 | ruby: convert block size, memory size to unsigned | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Cycles in MessageBuffer | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Cycles in Memory Controller | Nilay Vaish |
| 2013-02-10 | ruby: Replace Time with Cycles in SequencerMessage | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Cycles in Message class | Nilay Vaish |
| 2013-02-10 | ruby: replaces Time with Cycles in many places | Nilay Vaish |
| 2013-02-10 | base: add some mathematical operators to Cycles class | Nilay Vaish |
| 2013-02-10 | ruby: modifies histogram add() function | Nilay Vaish |
| 2013-02-10 | ruby: record fully busy cycle with in the controller | Nilay Vaish |
| 2013-02-10 | base: Fix broken IPython argument handling | Andreas Sandberg |
| 2013-01-31 | sim: remove unused struct priority_compare | Nilay Vaish |
| 2013-01-31 | ruby: correct computation of number of bits required for address | Nilay Vaish |
| 2013-01-31 | mem: Add comments for the DRAM address decoding | Andreas Hansson |
| 2013-01-31 | mem: Add DDR3 and LPDDR2 DRAM controller configurations | Andreas Hansson |
| 2013-01-31 | mem: Add tTAW and tFAW to the SimpleDRAM model | Ani Udipi |
| 2013-01-31 | mem: Separate out the different cases for DRAM bus busy time | Andreas Hansson |
| 2013-01-28 | cache: remove drainManager because it's not used | Anthony Gutierrez |
| 2013-01-28 | ruby: remove get_time() | Nilay Vaish |
| 2013-01-28 | ruby: remove call to curCycle in panic() | Nilay Vaish |
| 2013-01-24 | branch predictor: move out of o3 and inorder cpus | Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E) |
| 2013-01-22 | o3 cpu: fix zero reg problem | Andrea Pellegrini |
| 2013-01-22 | x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch | Nilay Vaish |
| 2013-01-19 | O3 IEW: Make incrWb and decrWb clearer | Joel Hestness |
| 2013-01-17 | ruby: remove calls to g_system_ptr->getTime() | Nilay Vaish |
| 2013-01-15 | x86 cpuid: enable clflush | Nilay Vaish |
| 2013-01-15 | x86: implements fsin, fcos instructions | Nilay Vaish |
| 2013-01-15 | x86: implements emms instruction | Nilay Vaish |
| 2013-01-15 | x86: implement fabs, fchs instructions | Nilay Vaish |
| 2013-01-14 | ruby sequencer: converts cycles to ticks in deadlock panic() | Malek Musleh |
| 2013-01-14 | Ruby: remove reference to g_system_ptr from class Message | Nilay Vaish |
| 2013-01-14 | Ruby: use ClockedObject in Consumer class | Nilay Vaish |
| 2013-01-14 | scons: Address clang 3.2 compilation error | Andreas Hansson |
| 2013-01-12 | base simple cpu: removes commented out code about cache ops | Nilay Vaish |
| 2013-01-12 | x86: Changes to decoder, corrects 9376 | Nilay Vaish |
| 2013-01-08 | util: add m5_fail op. | Lluís Vilanova |
| 2013-01-08 | sim: Fix early termination in multi-core simulation under SE mode. | Tao Zhang |
| 2013-01-08 | arm: add access syscall for ARM SE mode | Mitch Hayenga |
| 2013-01-08 | mem: Make LL/SC locks fine grained | Mitch Hayenga |
| 2013-01-08 | mem: Fix use-after-free bug | Mitch Hayenga |
| 2013-01-07 | dev: Fix infinite recursion in DMA devices | Andreas Sandberg |
| 2013-01-07 | stats: Fix swig wrapping for Tick in stats | Sascha Bischoff |
| 2013-01-07 | cpu: Unify the serialization code for all of the CPU models | Andreas Sandberg |
| 2013-01-07 | cpu: Flush TLBs on switchOut() | Andreas Sandberg |
| 2013-01-07 | mem: Fix guest corruption when caches handle uncacheable accesses | Andreas Sandberg |
| 2013-01-07 | cpu: Rewrite O3 draining to avoid stopping in microcode | Andreas Sandberg |
| 2013-01-07 | cpu: Make sure that a drained atomic CPU isn't executing ucode | Andreas Sandberg |
