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AgeCommit message (Expand)Author
2017-08-30arch-sparc: Add a FaultVals instantiation for VecDisabledAndreas Sandberg
2017-08-30arch-alpha: Add missing overridesAndreas Sandberg
2017-08-30python: Make GlobalExitEvent.getCode() return an intAndreas Sandberg
2017-08-30cpu-o3: fix data pkt initialization for split loadMatthias Hille
2017-08-28x86: Use the new CondInst format for moves to/from control registers.Gabe Black
2017-08-28x86: Add a "CondInst" format for conditionally decoded instructions.Gabe Black
2017-08-12dev: Fix an IDE error check.Gabe Black
2017-08-08mem-cache: Delete squashed HWPrefetchesPau Cabre
2017-08-02base: Give more information when setting up asynchronous IO fails.Gabe Black
2017-08-01arch-arm: Use named constants for m5op instructionsAndreas Sandberg
2017-08-01sim: Use named constants for pseudo opsAndreas Sandberg
2017-08-01kvm, arm: Switch to the device EQ when accessing ISA devicesAndreas Sandberg
2017-08-01kvm: Add a helper method to access device event queuesAndreas Sandberg
2017-08-01cpu, kvm: Fix deadlock issue when resuming a drained systemAndreas Sandberg
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
2017-07-20sim: Prevent segfault in the wakeCpu m5op if id is invalidJose Marinho
2017-07-19cpu: Add missing rename of vector registers in the O3 CPURekai Gonzalez-Alberquilla
2017-07-17cpu,o3: Fixed checkpointing bug occuring in the o3 CPUAnouk Van Laer
2017-07-17sim, x86: Make clone a virtual functionSean Wilson
2017-07-17x86: Add stats to X86 TLBSwapnil Haria
2017-07-17riscv: Define register index constants using literalsAlec Roelke
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
2017-07-14riscv: Add unused attribute to some registers.hh constantsAlec Roelke
2017-07-13arch-arm: fix ldm of pc interswitching branchGedare Bloom
2017-07-12ruby: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12arm: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12dev: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12net: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12testers: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12kvm, mem: Refactor some Event subclasses into lambdasSean Wilson
2017-07-12cpu: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12gpu-compute: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12sim, gdb: Refactor some Event subclasses into lambdasSean Wilson
2017-07-12mips, x86: Refactor some Event subclasses into lambdasSean Wilson
2017-07-12cpu, sim: Add param to force CPUs to wait for GDBJose Marinho
2017-07-11arch-riscv: Add support for compressed extension RV64CAlec Roelke
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke
2017-07-10dev-arm: Add ID registers to the GIC modelJose Marinho
2017-07-10arch-arm: Support PMU evens in the 0x4000-0x4040 rangeJose Marinho
2017-07-10dev-arm: Don't unconditionally overwrite bootloader paramsJose Marinho
2017-07-10dev: Fix OnIdle test in DmaReadFifoRohit Kurup
2017-07-10dev: Fix address type promotion issues in VirtIO devicesSascha Bischoff
2017-07-10sim: Fix clashing stat names in TickedObject and TickedJose Marinho
2017-07-07kvm, arm: don't create interrupt events while saving GIC stateCurtis Dunham
2017-07-07kvm, arm: Don't forward IRQ/FIQ when using the kernel's GICAndreas Sandberg
2017-07-05arch: ISA parser additions of vector registersRekai Gonzalez-Alberquilla
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05arch: added generic vector registerRekai Gonzalez-Alberquilla
2017-07-05cpu: Result refactoringRekai Gonzalez-Alberquilla