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AgeCommit message (Expand)Author
2006-12-21Expose the C++ event queue to python via the python functionNathan Binkert
2006-12-21styleNathan Binkert
2006-12-21Create a wrapper function to more easily add swig stuff to the buildNathan Binkert
2006-12-21move the swig initialization calls from src/sim/main.cc toNathan Binkert
2006-12-20don't use (*activeThreads).begin(), use activeThreads->blah().Nathan Binkert
2006-12-20Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
2006-12-20<scold> Make sure that variables are always initalized! </scold>Nathan Binkert
2006-12-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
2006-12-19Merge zizzer:/bk/newmemAli Saidi
2006-12-19fix twinx loads a little bitAli Saidi
2006-12-18Streamline Cache/Tags interface: get rid of redundant functions,Steve Reinhardt
2006-12-18No need to template prefetcher on cache TagStore type.Steve Reinhardt
2006-12-18Get rid of generic CacheTags object (fold back into Cache).Steve Reinhardt
2006-12-18Fix unittest compilesNathan Binkert
2006-12-18cast chars to int when we want to print integers so we get a numberNathan Binkert
2006-12-18move the twinx loads to the correct opcode and add asis 0x24 and 0x27Ali Saidi
2006-12-17Compilation fixes.Gabe Black
2006-12-17Added in the extended twin load formatGabe Black
2006-12-16Merge zizzer:/bk/newmemGabe Black
2006-12-16Merge zizzer:/bk/sparcfs/Gabe Black
2006-12-16Support for twin loads.Gabe Black
2006-12-16Compiler error fix.Gabe Black
2006-12-15Merge zizzer:/bk/newmemLisa Hsu
2006-12-15small change to eliminate address range overlap.Lisa Hsu
2006-12-15little fixes i noticed while searching for reason for address range issues (b...Lisa Hsu
2006-12-15Merge zizzer:/bk/sparcfsLisa Hsu
2006-12-15some small general fixes to make everythign work nicely with other ISAs, now ...Lisa Hsu
2006-12-15tlb.cc:Lisa Hsu
2006-12-15Use my range_map to speed up findPort() in the bus. The snoop code could stil...Ali Saidi
2006-12-15Optimized the TLB translations with some cachingAli Saidi
2006-12-14flesh out twinx asisAli Saidi
2006-12-13Split CachePort class into CpuSidePort and MemSidePortSteve Reinhardt
2006-12-13Merge zizzer:/bk/newmemLisa Hsu
2006-12-13fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.Lisa Hsu
2006-12-13Merge zizzer:/bk/newmemLisa Hsu
2006-12-13Merge zizzer:/bk/sparcfsLisa Hsu
2006-12-12Merge zizzer:/bk/newmemLisa Hsu
2006-12-12Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-12-12Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)Ali Saidi
2006-12-12Allow for multiple redirects to happen on a single cycle (only the one for th...Kevin Lim
2006-12-12Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(In...Steve Reinhardt
2006-12-12Get rid of unused lock code.Steve Reinhardt
2006-12-11Fix up in case a req hasn't yet been generated for this instruction (if there...Kevin Lim
2006-12-11Fix for fetch to use the icache's block size to generate proper access size.Kevin Lim
2006-12-09Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2006-12-09fix lisa's hand mergeAli Saidi
2006-12-09Merge zizzer:/bk/sparcfsAli Saidi
2006-12-09Allocate the correct number of global registersAli Saidi
2006-12-08Merge zizzer:/bk/sparcfsLisa Hsu
2006-12-08mostly implemented SOFTINT relevant interrupt stuff.Lisa Hsu
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