Age | Commit message (Collapse) | Author |
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/SConscript:
SCCS merged
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extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
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"generic" devices are dependent on some of those files. That will either need to change, or most likely those devices will have to be considered architecture dependent.
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rename : src/dev/tsunami.cc => src/dev/alpha/tsunami.cc
rename : src/dev/tsunami.hh => src/dev/alpha/tsunami.hh
rename : src/dev/tsunami_cchip.cc => src/dev/alpha/tsunami_cchip.cc
rename : src/dev/tsunami_cchip.hh => src/dev/alpha/tsunami_cchip.hh
rename : src/dev/tsunami_io.cc => src/dev/alpha/tsunami_io.cc
rename : src/dev/tsunami_io.hh => src/dev/alpha/tsunami_io.hh
rename : src/dev/tsunami_pchip.cc => src/dev/alpha/tsunami_pchip.cc
rename : src/dev/tsunami_pchip.hh => src/dev/alpha/tsunami_pchip.hh
rename : src/dev/tsunamireg.h => src/dev/alpha/tsunamireg.h
extra : convert_revision : ffbb6fd93341d2623a6932bf096019b8976da694
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but isn't tested. Other architectures will not.
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extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
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from TheISA:: rather than AlphaISA::
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extra : convert_revision : 17c143d3cbc2f58a7a9d01366a8f649810ff7f33
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Alpha and SPARC and put SConscripts in them.
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rename : src/base/kgdb.h => src/arch/alpha/kgdb.h
rename : src/dev/alpha_access.h => src/dev/alpha/access.h
rename : src/dev/alpha_console.cc => src/dev/alpha/console.cc
rename : src/dev/alpha_console.hh => src/dev/alpha/console.hh
extra : convert_revision : a7dd466308cb83edc40528689aacb72413089cdf
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src/SConscript:
remove pcifake and tsunami fake from sconscript
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
combine badaddr and isa fake into one
src/python/m5/objects/Pci.py:
remove pcifake
src/python/m5/objects/Tsunami.py:
make badaddr derive from isafake
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extra : convert_revision : 91470db60aa1de6b85827304e27bd3414cc9d8d1
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src/cpu/base.cc:
Move clock phase drift code to the base CPU so that any CPU model can use it.
src/cpu/base.hh:
Added two functions to help get the next cycle the CPU should be scheduled.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Use the function now in BaseCPU.
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extra : convert_revision : 444494b66ffc85fc473c23f57683c5f9458ad80c
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src/cpu/o3/lsq_unit_impl.hh:
Be sure to initialize pointer to NULL.
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extra : convert_revision : 917d5119e4bd8eae10959ed07069d8c694315c7a
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into zeep.pool:/z/saidi/work/m5.newmem
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SConstruct:
Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
solaris doesn't have random(), so use rint with the correct rounding mode
if we're compiling on solaris
src/base/stats/flags.hh:
u_int32_t??
src/base/time.hh:
grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
we don't need to include stdint here
src/sim/byteswap.hh:
the method to detect endianness on Solaris is a little more complex...
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because apparently you need an xc for that and not a tc. Cleaned up the TrapInstruction fault in light of this.
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can access it.
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PowerOnReset fault to kick start the CPU.
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could be improved and syscalls could be called from the trap's invoke method.
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src/arch/sparc/faults.cc:
Moved some code here from miscregfile.cc
src/arch/sparc/miscregfile.cc:
Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc
src/arch/sparc/miscregfile.hh:
readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect.
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system.cc
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are in PAL mode, however.
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records when interrupts are requested, and returns an interrupt to execute if the
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
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should be able to boot into Linux with caches on after this change.
src/mem/bus.cc:
src/mem/bus.hh:
Bus now will be setup with a default responder, unless the user overrides it. This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
Bus now has a default responder for FS mode if the user doesn't override it. It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
Add bad address device. Also record when the user has specified their own default responder.
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src/mem/cache/base_cache.cc:
Have caches return a new functional port whenever asked for them. I'm pretty sure this is desired behavior. Ron can correct me if it's not.
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extra : convert_revision : e1fadf895a7d714968128ff900d10e86fde53387
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src/cpu/simple_thread.cc:
Fix up port handling to share code.
src/cpu/thread_state.cc:
Separate code off into a function.
src/cpu/thread_state.hh:
Make a separate function that will get the CPU's memory's functional port.
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extra : convert_revision : 96a9bb3c5e4b9ba5511678c0fd17f0017c8cd312
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src/cpu/simple_thread.cc:
This function should have been deleted from an earlier push.
src/cpu/simple_thread.hh:
Delete this function; it's now in thread_state.hh/.cc.
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extra : convert_revision : f78dcf9c2b388418030d48d0ea4911c8b8b1f5ff
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src/arch/alpha/utility.hh:
For now makeExtMI will be specific to the ISA.
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extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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--HG--
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file functions to not take faults
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corresponding to an IPR is readable or writable.
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code all over the place.
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