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Add support for a memory mapped m5op interface. When enabled, the TLB
intercepts accesses in the 64KiB region designated by the
ArmTLB.m5ops_base parameter. An access to this range maps to a
specific m5op call. The upper 8 bits of the offset into the range
denote the m5op function to call and the lower 8 bits denote the
subfunction.
Change-Id: I55fd8ac1afef4c3cc423b973870c9fe600a843a2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2964
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The state transfer code wasn't reading back PSTATE correctly from the
CPU prior to updating the thread context and was incorreclty writing
the register as a 32-bit value when updating KVM. Correctly read back
the state before updating gem5's view of PSTATE and cast the value to
a uint64_t.
Change-Id: I0a6ff5b77b897c756b20a20f65c420f42386360f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2963
Reviewed-by: Rahul Thakur <rjthakur@google.com>
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The value of that variable can be computed more directly and more locally
to where it's consumed.
Change-Id: I5ca1f732a34e22d4dae2aeb6ee7fc8adebe1caa0
Reviewed-on: https://gem5-review.googlesource.com/2981
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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For Value() nodes, the get_contents() method and the get_text_contents()
method are just aliases to the same thing, both of which return a value
which has already been converted using str(). The str() which was included
explicitly in the SConscript was redundant, except that it showed that the
value from get_contents was being treated as a string. To avoid the
redundancy but to still leave a hint to the value's type, this change
converts those bits of code to use get_text_contents() and removes the
str().
Change-Id: I8f7da9b652f749e741b553c9a0e2248ae15ec3ca
Reviewed-on: https://gem5-review.googlesource.com/3084
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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That clues scons in to the fact that the contents of the target of that
function depends on the value of that construction variable.
Change-Id: I803322ea1a178152da3d95dffffe20acd4271c88
Reviewed-on: https://gem5-review.googlesource.com/3083
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This commit fixes a stack-buffer underflow
by fixing the way the array is indexed.
Change-Id: I44400e2b99a2f8e1f48f673cd110b9dcd6480a72
Reviewed-on: https://gem5-review.googlesource.com/3040
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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We're already visiting each of the environments, there's no reason to
track them all and then set up test SConscripts on a second pass.
Change-Id: I2d1166f58ac907e874d6ad5de7bd53ff7ad645f8
Reviewed-on: https://gem5-review.googlesource.com/2980
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Remove SWIG-specific Python code.
Change-Id: If1d1b253d84021c9a8f9a64027ea7a94f2336dff
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2922
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
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Remove SWIG guards and SWIG-specific C++ code.
Change-Id: Icaad6720513b6f48153727ef3f70e0dba0df4bee
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2921
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
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Use the PyBind11 wrapping infrastructure instead of SWIG to generate
wrappers for functionality that needs to be exported to Python. This
has several benefits:
* PyBind11 can be redistributed with gem5, which means that we have
full control of the version used. This avoid a large number of
hard-to-debug SWIG issues we have seen in the past.
* PyBind11 doesn't rely on a custom C++ parser, instead it relies on
wrappers being explicitly declared in C++. The leads to slightly
more boiler-plate code in manually created wrappers, but doesn't
doesn't increase the overall code size. A big benefit is that this
avoids strange compilation errors when SWIG doesn't understand
modern language features.
* Unlike SWIG, there is no risk that the wrapper code incorporates
incorrect type casts (this has happened on numerous occasions in
the past) since these will result in compile-time errors.
As a part of this change, the mechanism to define exported methods has
been redesigned slightly. New methods can be exported either by
declaring them in the SimObject declaration and decorating them with
the cxxMethod decorator or by adding an instance of
PyBindMethod/PyBindProperty to the cxx_exports class variable. The
decorator has the added benefit of making it possible to add a
docstring and naming the method's parameters.
The new wrappers have the following known issues:
* Global events can't be memory managed correctly. This was the
case in SWIG as well.
Change-Id: I88c5a95b6cf6c32fa9e1ad31dfc08b2e8199a763
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Andrew Bardsley <andrew.bardsley@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2231
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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A previous change forced scons to spawn child processes by exec-ing it
directly rather than going through the shell because the command line
length would be too long for the shell to handle. Now that incremental
linking should keep the command line lengths more under control, that
change should no longer be necessary.
Change-Id: I9e82a62083afd1414324a7fd697bd6d4b76367ae
Reviewed-on: https://gem5-review.googlesource.com/2947
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The groups won't be perfectly balanced or optimally planned, but this
requires no thought and breaks the object files down into a reasonable
number of reasonably sized groups.
Change-Id: I6542fc807aaf356a9be751093f68e2e29f0b1586
Reviewed-on: https://gem5-review.googlesource.com/2946
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The groups will be linked together into intermediate partially linked
object files. Right now the hierarchy is assumed to be flat, but with some
effort it could be extended to allow truly hierarchical linking.
Change-Id: I77b77710554e5f05e8b00720a0170afaf4afac2d
Reviewed-on: https://gem5-review.googlesource.com/2945
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I94e15ae79f0e73692d882f62fd2b7bf45cf0c841
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2900
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Add a case for the ATA command ATAPI_IDENTIFY_DEVICE.
This avoids the panic: Unsupported ATA command when booting a recent Linux
kernel. This was tested on 4.8.13.
Change-Id: Ib297a2c02da0730d8698c59801254dd0f5ee9f7f
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/2863
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
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When a branch micro-op belongs to a flow and the micro-op does not change
the nPC and just updates the nuPC (like a 'rep movs' flow), branching()
function always returns not-taken no matter actual micro-branch outcome.
Provided fix adds to the equation nuPC attribute checking since these kind
of branch micro-op only updates that pointer.
This issue has been found while debugging the performance of a copy-loop
implemented with memcopy function. Without the fix, 'rep movss' internal
micro-branch was always predicted as not-taken causing an squash event
after every branch micro-branch execution.
Using the provided test, branch mispredition went from 1922 without the fix
to 7.
Change-Id: I1bcbefae26aef47e3135817ef99b53d0ea0a98fa
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The command line can be too long, causing bash to choke. This means we can't
use any shell syntax like shell variables or redirection when linking, but
that should be easy to avoid.
Change-Id: Ie6c8ecab337cef6bd3c7e403346ced06f46f0993
Reviewed-on: https://gem5-review.googlesource.com/2780
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Allow global stats such as sim_seconds in power equations to make it
possible to convert from event stats to rate stats.
Change-Id: I429abe0ffadc0dbd162eb39e0897143be472ef65
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2720
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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This patch fixes a bug where increasing the mmap region too much causes
it to run into already-allocated memory, which causes gem5 to fail an
assertion. Previously, the stack was incorrectly set up such that the
end of the mmap region and the top of the stack were the same address
and both would grow downward. With this patch, the top of the stack has
been separated from the end of mmap and moved up, and the mmap region
now grows upward instead of downward.
[Rebase to master branch and remove dependencies.]
Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520
Reviewed-on: https://gem5-review.googlesource.com/2680
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: Iab5070fc9b666fcb5b49b0e2b99a4a1605b3b721
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
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There is currently no good way of extracting the current operating
voltage in MathExprPowerModels. This change adds a magic variable,
'voltage', that can be referenced from such expressions to get the
current operating voltage.
Change-Id: Ice3c9a4a221921a542de5da52f83f3f88862d246
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2662
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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MathExprPower model currently doesn't print any useful error messages
if an expression fails to evaluate. To add insult to injury, the model
only detects a failure when dumping stats and not at
initialization. This change adds a verification step in startup() that
ensures that all of the referenced stats actually exist.
Change-Id: I8f71c73341578d5882c8d93e482f5383fbda5f1d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2661
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Multiple outstanding DMA requests introduced new DMA states that didn't
be considered into slicc code. This patch implements the missed DMA state
changes on MOESI_CMP_directory protocol.
Change-Id: I700d441d76556b7e77e0d507904af6ec6ba59cc2
Signed-off-by: Michael LeBeane <michael.lebeane@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/2380
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Some of the functions in the Linux toolchain that allocate memory make
use of paired LR and SC instructions, which didn't work properly for
that toolchain. This patch fixes that so attempting to use those
functions doesn't cause an endless loop of failed SC instructions.
Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7
Reviewed-on: https://gem5-review.googlesource.com/2340
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode. This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it. Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.
[Update for recent changes to MemState to add accessors and mutators to
get its members.]
Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
Reviewed-on: https://gem5-review.googlesource.com/2305
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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This patch adds support for debugging with remote GDB to RISC-V. Using
GDB compiled with the RISC-V GNU toolchain, it is possible to pause
and continue execution, view debugging information, etc. As with the
rest of RISC-V, this does not support full-system mode.
Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d
Reviewed-on: https://gem5-review.googlesource.com/2304
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0xFFFFFFFFFFFFFFFF), an assert would fail during address translation and
gem5 would crash. This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen. Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.
[Update creation of page table fault to use make_shared.]
[Add comment explaining the change and assertion that the memory request
isn't zero size.]
Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Reviewed-on: https://gem5-review.googlesource.com/2345
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Sometimes an ld instruction will be split across a
cache boundary. Previously RISC-V was set to not
allow this. This patch fixes that.
Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
Reviewed-on: https://gem5-review.googlesource.com/2341
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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This also allows checkpointing of a Kvm GIC via the Pl390 model.
Change-Id: Ic85d81cfefad630617491b732398f5e6a5f34c0b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2444
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
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The Binary Point Register (BPR) specifies which bits belong to the
group priority field (which are used for preemption) and which to the
subpriority field (which are ignored for preemption).
Change-Id: If51e669d23b49047b69b82ab363dd01a936cc93b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2443
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
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The aforementioned registers (Interrupt Processor Targets Registers) are
banked per-CPU, but are read-only. This patch eliminates the per-CPU
storage of these values that are simply computed.
Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2442
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
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Change-Id: I696703418506522ba90df5c2c4ca45c95a6efbea
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2441
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
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Instructions that use the coprocessor interface check the current
program status to determine whether the current context has the
priviledges to read from/write to the coprocessor. Some modes allow
the execution of coprocessor instructions, some others do not allow it,
while some other modes are unexpected (e.g., executing an AArch32
instruction while being in an AArch64 mode).
Previously we would unconditionally trigger a panic if we were in an
unexpected mode. This change removes the panic and replaces it
with an Undefined Instruction fault that triggers if and when a
coprocessor instruction commits in an unexpected mode. This allows
speculative coprocessor instructions from unexpected modes to execute
but prevents them from gettting committed.
Change-Id: If2776d5bae2471cdbaf76d0e1ae655f501bfbf01
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2281
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
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A completed write to a memory location that is Write-Through Cacheable
has to be visible to an external observer without the need of explicit
cache maintenance. This change adds support for Write-Through
Cacheable Normal memory and treats it as Non-cacheable. This incurs a
small penalty as accesses to the memory do not fill in the cache but
does not violate the properties of the memory type.
Change-Id: Iee17ef9d952a550be9ad660b1e60e9f6c4ef2c2d
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2280
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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There are cases where Drainable objects need to create new objects in
Drainable::resume(). In such cases, the local drain state will be
inherited from the DrainManager. We currently set the state to Running
as soon as we start resuming the simulator. This means that new
objects are created in the Running state rather than the Drained
state, which the resume code assumes. Depending on the traversal order
in DrainManager::resume(), this sometimes triggers a panic because the
object being resumed is in the wrong state.
This change introduces a new drain state, Resuming, that the
DrainManager enters as soon as it starts resuming the
simulator. Objects that are created while resuming are created in this
state. Such objects are then resumed in a subsequent pass over the
list of Drainable objects that need to be resumed. Once all objects
have been resumed, the simulator enters the Running state.
Change-Id: Ieee8645351ffbdec477e9cd2ff86fc795e459617
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2600
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
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The kernel and gem5 derive MPIDR values from CPU IDs in slightly
different ways. This means that guests running in a multi-CPU setup
sometimes fail to bring up secondary CPUs. Fix this by overriding the
MPIDR value in virtual CPUs just after they have been instantiated.
Change-Id: I916d44978a9c855ab89c80a083af45b0cea6edac
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2461
Reviewed-by: Weiping Liao <weipingliao@google.com>
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The generic timer sometimes needs to access global state. This can
lead to race conditions when simulating a multi-core KVM system where
each core lives in its own thread. In that case, the setMiscReg and
readMiscReg methods are called from the thread owning the CPU and not
the global device thread.
Change-Id: Ie3e982258648c8562cce0b30a0c122dfbfaf42cd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2460
Reviewed-by: Weiping Liao <weipingliao@google.com>
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When setting the size of a PCI BAR, the kernel only supports powers of
two (as per the PCI spec). Previously, the size was incorrectly read
by the kernel, and the address ranges assigned to the PCI devices
could overlap, resulting in gem5 crashes. We now round up to the next
power of two.
Kudos to Sergei Trofimov who helped to debug this issue!
Change-Id: I54ca399b62ea07c09d4cd989b17dfa670e841bbe
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Sergei Trofimov <sergei.trofimov@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2580
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
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VirtIO transport interfaces always expect a VirtIO device
pointer. However, there are cases (in particular when using VirtIO's
MMIO interface) where we want to instantiate an interface without a
device. Add a dummy device using VirtIO device ID 0 and no queues to
handle this use case.
Change-Id: I6cbe12fd403903ef585be40279c3b1321fde48ff
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2325
Reviewed-by: Weiping Liao <weipingliao@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Rename VIOPci -> VIOIface to avoid having a separate flag for the MMIO
interface.
Change-Id: I99f9210fa36ce33662c48537fd3992cd9a69d349
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2324
Reviewed-by: Weiping Liao <weipingliao@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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In arch/arm/faults.hh, template the static member vals require explicit
specialisation to avoid compiler warnings.
Change-Id: Ie404ccaa43269cb1bb819e33153e776abbf3a79b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I4c0de7c2a5b40c1a9f009ca12062cb108b450b04
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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Determine if gem5 is running in a batch environment by checking if
STDIN is wired to a TTY or not. If the simulator is running in a batch
environment, disable all listeners by default. This behavior can be
overridden using the --enable-listeners option.
Change-Id: I404c709135339144216bf08a2769c016c543333c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sean McGoogan <sean.mcgoogan@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2322
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The clone system call added in 236719892 relies on header files
from Linux systems. Obviously, this prevents compilation for
anyone using FreeBSD or Mac to compile the simulator. This
changeset is meant as a temporary fix to allow builds on
non-Linux systems until a proper solution is found.
Change-Id: I404cc41c588ed193dd2c1ca0c1aea35b0786fe4e
Reviewed-on: https://gem5-review.googlesource.com/2420
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I9ff21092876593237f919e9f7fb7283bd865ba2e
Reviewed-on: https://gem5-review.googlesource.com/2421
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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This change adds the ability to print a message at intervals
of committed instruction count to indicate progress in the
trace replay.
Change-Id: I8363502354c42bfc52936d2627986598b63a5797
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2321
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The Pl390::getAddrRanges() method should have been flagged using the
override keyword. Other methods in this class already use the override
keyword, so this results in a warning about inconsistent override
usage when compiling using clang.
Change-Id: I17449687a8e074262232562487b58c96466bd54e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
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The GIC model currently adds a delay to interrupts when posting them
to a target CPU. This means that an interrupt signal will be
represented by an event for a short period of time. We currently
ignore this when draining and serialize the tick when the interrupt
will fire. Upon loading the checkpoint, the simulated GIC reschedules
the pending events. This behaviour is undesirable when we implement
support for switching between in-kernel GIC emulation and gem5 GIC
emulation. In that case, the (kernel) GIC model gets a lot simpler if
we don't need to worry about in-flight interrupts from the gem5 GIC.
This changeset adds a draining check to force the GIC into a state
where all interrupts have been delivered prior to checkpointing/CPU
switching. It also removes the now redundant serialization of
interrupt events.
Change-Id: I8b8b080aa291ca029a3a7bdd1777f1fcd5b01179
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2331
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Lots of minor cleaups:
* Make cached params const
* Don't serialize params
* Use AddrRange to represent the distributor and CPU address spaces
* Store a const AddrRangeList of all PIO ranges
Change-Id: I40a17bc3a38868fb3b8af247790e852cf99ddf1d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2330
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I02719f3572f6665cace1eb5681f297dcde9e71ce
Reviewed-on: https://gem5-review.googlesource.com/2271
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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