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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
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path:
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src
Age
Commit message (
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Author
2013-02-15
loader: add a flattened device tree blob (dtb) object
Anthony Gutierrez
2013-02-15
arm: fix a page table walker issue where a page could be translated multiple ...
Mrinmoy Ghosh
2013-02-15
cpu: Document exec trace flags
Andreas Sandberg
2013-02-15
dev: Use the correct return type for disk offsets
Andreas Sandberg
2013-02-15
cpu: Avoid duplicate entries in tracking structures for writes to misc regs
Geoffrey Blake
2013-02-15
cpu: Fix rename mis-handling serializing instructions when resource constrained
Geoffrey Blake
2013-02-15
ARM: Postpones creation of framebuffer output file until it is actually used.
Chris Emmons
2013-02-15
mem: Tighten up cache constness and scoping
Andreas Hansson
2013-02-15
base: Add warn() and inform() to m5.utils for use from python
Sascha Bischoff
2013-02-15
o3: fix tick used for renaming and issue with range selection
Matt Horsnell
2012-10-25
arm: Don't export private GIC methods
Andreas Sandberg
2012-10-25
arm: Create a GIC base class and make the PL390 derive from it
Andreas Sandberg
2013-02-15
sim: Add a system-global option to bypass caches
Andreas Sandberg
2013-02-15
cpu: Refactor memory system checks
Andreas Sandberg
2013-02-15
config: Move CPU handover logic to m5.switchCpus()
Andreas Sandberg
2013-02-15
cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
Andreas Sandberg
2013-02-15
cpu: Add CPU metadata om the Python classes
Andreas Sandberg
2013-02-15
arm: fix some fp comparisons that worked by accident.
Ali Saidi
2013-02-15
cpu: include set in o3/commit_impl.
Ali Saidi
2013-02-15
ARM: Fix an issue with clang generating wrong code.
Ali Saidi
2013-02-15
cpu: fix case with o3 cpu blocking and unblocking decode in cycle
Ali Saidi
2013-02-15
cpu: Fix a livelock in the o3 cpu.
Ali Saidi
2013-02-10
base: Add support for newer versions of IPython
Andreas Sandberg
2013-02-14
Ruby: Fix compilation errors on gcc 4.7 and clang 3.2
Andreas Hansson
2013-02-10
ruby: MI protocol: add a missing transition
Nilay Vaish
2013-02-10
ruby: enable multiple clock domains
Nilay Vaish
2013-02-10
ruby: replace Time with Cycles (final patch in the series)
Nilay Vaish
2013-02-10
ruby: replace Time with Cycles in garnet fixed and flexible
Nilay Vaish
2013-02-10
ruby: replace Time with Tick in replacement policy classes
Nilay Vaish
2013-02-10
ruby: convert block size, memory size to unsigned
Nilay Vaish
2013-02-10
ruby: replace Time with Cycles in MessageBuffer
Nilay Vaish
2013-02-10
ruby: replace Time with Cycles in Memory Controller
Nilay Vaish
2013-02-10
ruby: Replace Time with Cycles in SequencerMessage
Nilay Vaish
2013-02-10
ruby: replace Time with Cycles in Message class
Nilay Vaish
2013-02-10
ruby: replaces Time with Cycles in many places
Nilay Vaish
2013-02-10
base: add some mathematical operators to Cycles class
Nilay Vaish
2013-02-10
ruby: modifies histogram add() function
Nilay Vaish
2013-02-10
ruby: record fully busy cycle with in the controller
Nilay Vaish
2013-02-10
base: Fix broken IPython argument handling
Andreas Sandberg
2013-01-31
sim: remove unused struct priority_compare
Nilay Vaish
2013-01-31
ruby: correct computation of number of bits required for address
Nilay Vaish
2013-01-31
mem: Add comments for the DRAM address decoding
Andreas Hansson
2013-01-31
mem: Add DDR3 and LPDDR2 DRAM controller configurations
Andreas Hansson
2013-01-31
mem: Add tTAW and tFAW to the SimpleDRAM model
Ani Udipi
2013-01-31
mem: Separate out the different cases for DRAM bus busy time
Andreas Hansson
2013-01-28
cache: remove drainManager because it's not used
Anthony Gutierrez
2013-01-28
ruby: remove get_time()
Nilay Vaish
2013-01-28
ruby: remove call to curCycle in panic()
Nilay Vaish
2013-01-24
branch predictor: move out of o3 and inorder cpus
Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-22
o3 cpu: fix zero reg problem
Andrea Pellegrini
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