gem5 - gem5

Age	Commit message (Collapse)	Author
2010-06-02	ARM: Make MPIDR return 0 and ignore writes.	Gabe Black

2010-06-02	ARM: Implement the VCMPE instruction.	Gabe Black

2010-06-02	ARM: Fix vcvtr so that it uses the rounding mode in the FPSCR.	Gabe Black

2010-06-02	ARM: Fix saturation of VCVT from fp to integer.	Gabe Black

2010-06-02	ARM: Compensate for ARM's underflow coming from -before- rounding, but x86's ↵	Gabe Black
	after.
2010-06-02	ARM: Implement flush to zero for destinations as well.	Gabe Black

2010-06-02	ARM: Fix up nans to match ARM's expected behavior.	Gabe Black

2010-06-02	ARM: Set the value of the MVFR0 and MVFR1 registers.	Gabe Black

2010-06-02	ARM: Implement flush to zero mode for VFP, and clean up some corner cases.	Gabe Black

2010-06-02	ARM: Add barriers that make sure FP operations happen where they're supposed to.	Gabe Black

2010-06-02	ARM: Implement the version of VCVT float to int that rounds towards zero.	Gabe Black

2010-06-02	ARM: Implement the floating/fixed point VCVT instructions.	Gabe Black

2010-06-02	ARM: Add code to extract and record VFP exceptions.	Gabe Black

2010-06-02	ARM: Implement the VFP version of VCMP.	Gabe Black

2010-06-02	ARM: Add support for VFP vector mode.	Gabe Black

2010-06-02	ARM: Introduce new VFP base classes that are optionally microops.	Gabe Black

2010-06-02	ARM: Implement VCVT between double and single width FP.	Gabe Black

2010-06-02	ARM: Implement vcvt between int and fp. Ignore rounding.	Gabe Black

2010-06-02	ARM: Consolidate the VFP register index computation code.	Gabe Black

2010-06-02	ARM: Implement the VFP negated multiplies.	Gabe Black

2010-06-02	ARM: Implement the VFP versions of VMLA and VMLS.	Gabe Black

2010-06-02	ARM: Implement the VFP version of vdiv and vsqrt.	Gabe Black

2010-06-02	ARM: Implement the VFP version of vsub.	Gabe Black

2010-06-02	ARM: Implement the VFP version of vadd.	Gabe Black

2010-06-02	ARM: Implement the VFP version of vabs.	Gabe Black

2010-06-02	ARM: Implement the VFP version of vneg.	Gabe Black

2010-06-02	ARM: Implement the VFP version of vmul.	Gabe Black

2010-06-02	ARM: Move the VFP data operation decode into a function.	Gabe Black

2010-06-02	ARM: Implement and update the DFSR and IFSR registers on faults.	Gabe Black

2010-06-02	ARM: Make integer division by zero return a fault.	Gabe Black

2010-06-02	ARM: Add in some missing SCTLR fields.	Gabe Black

2010-06-02	ARM: Decode ARM unconditional MRC and MCR instructions.	Gabe Black

2010-06-02	ARM: Move the CP15 decode block into a function.	Gabe Black

2010-06-02	ARM: Decode the unconditional version of ARM fp instructions.	Gabe Black

2010-06-02	ARM: Move the FP decode blocks into functions.	Gabe Black

2010-06-02	ARM: Warn/ignore when TLB maintenance operations are performed.	Gabe Black

2010-06-02	ARM: Handle accesses to TLBTR.	Gabe Black

2010-06-02	ARM: Handle accesses to the DACR.	Gabe Black

2010-06-02	ARM: Handle accesses to TTBR0 and TTBR1.	Gabe Black

2010-06-02	ARM: Convert the CP15 registers from MPU to MMU.	Gabe Black

2010-06-02	ARM: Add some support for wfi/wfe/yield/etc	Ali Saidi

2010-06-02	ARM: Move PC mode bits around so they can be used for exectrace	Ali Saidi

2010-06-02	ARM: Add a traceflag to print cpsr	Ali Saidi

2010-06-02	ARM: Undef instruction on invalid user CP15 access	Ali Saidi

2010-06-02	ARM: Decode the VSTR instruction.	Gabe Black

2010-06-02	ARM: Implement the vstr instruction.	Gabe Black

2010-06-02	ARM: BXJ should be BX when there is no J support	Ali Saidi

2010-06-02	ARM: Make sure macroops aren't interrupted midinstruction.	Gabe Black
	Do this by setting the delayed commit flag for all but the last microop.
2010-06-02	ARM: Fix the implementation of the VFP ldm and stm macroops.	Gabe Black
	There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02	Simple CPU: Make the FloatRegs trace flag do something.	Gabe Black