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2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
The x86 version doesn't do anything x86 specific, and so can be used generically in sim/pseudo_inst.(hh|cc) Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
The logic that determines which syscall to call was built into the implementation of faults/exceptions or even into the instruction decoder, but that logic can depend on what OS is being used, and sometimes even what version, for example 32bit vs. 64bit. This change pushes that logic up into the Process objects since those already handle a lot of the aspects of emulating the guest OS. Instead, the ISA or fault implementations just notify the rest of the system that a nebulous syscall has happened, and that gets propogated upward until the process does something with it. That's very analogous to how a system call would work on a real machine. When a system call happens, the low level component which detects that should call tc->syscall(&fault), where tc is the relevant thread (or execution) context, and fault is a Fault which can ultimately be set by the system call implementation. The TC implementor (probably a CPU) will then have a chance to do whatever it needs to to handle a system call. Currently only O3 does anything special here. That implementor will end up calling the Process's syscall() method. Once in Process::syscall, the process object will use it's contextual knowledge to determine what system call is being requested. It then calls Process::doSyscall with the right syscall number, where doSyscall centralizes the common mechanism for actually retrieving and calling into the system call implementation. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I937ec1ef0576142c2a182ff33ca508d77ad0e7a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23176 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-12-10x86: Stop manually clearing RFLAGS.RF after a system call.Gabe Black
The system call stub KVM uses in SE mode to call the system call pseudo instruction which ultimately calls m5Syscall already uses sysret, and the implementation of sysret clears both the RF and VM bits itself. There's no reason to do that again explicitly here. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Id7b5417564e3f3492ba6efb8ed36fab2f4c38e09 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23175 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
Setting syscall args isn't really something we need to do in gem5, since that will be taken care of by the code actually calling the syscall. We just need to be able to retrieve the value it put there. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I0bb6d5d0207a7892414a722b3788cb70ee509582 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23174 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Stop using setSyscallArg to set argc and argv.Gabe Black
In Alpha and MIPS, the argc and argv values should be in what happens to be the first and second syscall argument registers, but that's not by definition. The process objects of both those ISAs know what registers to use intrinsically, so there's also no reason to call out to a helper method which acts as a part of the Process's interface to the rest of gem5. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Id8fa38ab1fc2ac6436e94ad41303439973fded10 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23173 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Add a wrapper/subclass for SyscallDesc which uses GuestABI.Gabe Black
This will let system call implementations take arguments naturally, and centrally defined, potentially complex, and ISA/context specific mechanisms will automatically gather the arguments and store any result. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I68d265e0bab5de372ba975e4c7e9bb2d968c80af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23172 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Add a mechanism to translate ABIs to call host funcs from a TC.Gabe Black
The guest ABI is specified as a template parameter. This makes it possible for host simcall handlers to be called through different ABIs which might be from different ISAs, or might be from different contexts within the same ISA (32 vs 64 bit, syscall vs. function vs. pseudo instrunction vs. semihosting call). Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I66a0f558e9c1f70a142b69b0dd95bd71e41d898b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23171 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Get rid of the now unused SyscallDesc flags and methods.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Icee18a4bd77a346d7f82ef4988651b753392d51e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23170 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I9bbffcc74ec4f3df4effa5c50f0a4a688c5b6016 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23169 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Reintroduce the ignoreWarnOnceFunc syscall handler.Gabe Black
Instead of just using warn_once, we'll gate each warning on a bool which is associated with the syscall desc pointer. To avoid having to keep warn once bookkeeping in every syscall desc, we put it in a map which is looked up at runtime. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I1dcce48de91b8a635f9f3df3bfc0ed6ba1291c4f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23168 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-12-10sim: Make the syscalls use the SyscallReturn suppression mechanism.Gabe Black
This, among other things, prevents them from needing to toggle global flags in the syscall desc table to control local behavior. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Idcef23766084f10d5205721b54a6768a850f7eb9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23167 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-12-10dev-arm: GenericTimer, configurable base and low freqsAdrian Herrera
Architecture states the system counter has a fixed base frequency provided in the first entry of the frequency modes table. Optionally, other lower frequencies may be specified in consecutive entries. This patch adds configurable frequencies to the GenericTimer model. The default base frequency is kept as the one that was previously hardcoded for backwards compatibility. The table is not recommended to be updated once the system is running. Change-Id: Icba0b340a0eb1cbb47dfe7d7e03b547af4570c60 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22425 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10dev-arm: GenericTimer, freq as 32-bit valueAdrian Herrera
The System Counter frequency is now a 32-bit value. This is consistent with CNTFRQ and CNTFRQ_EL0 register sizes. Change-Id: I39886a3767adbe9c58887b8b6d5f30ebc6035bcc Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22424 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Disambuiguate NumFloatV7ArchRegs usageGiacomo Travaglini
Sometimes NumFloatV7ArchRegs is used to specify the maximum number of AArch32 floating point registers. Sometimes it is just used for indexing a free register storage to be used by microcode. In that scenario, VecSpecialElem should be used, which is a index to the first available non architectural register for floating point. Change-Id: I4e84740701f0e7041cf1acad2afed471361c423a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23107 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Unify VLdmStm behaviour when reg out of indexGiacomo Travaglini
The generic VLdmStm class (modelling A32 VLDM/VSTM) is handling a wrong register list in a inconsistent way. Some instructions are opting for being decoded as Unknown, while others handle it inside the macro instruction constructor by manually adjusting the reglist. Those are two valid implementation of the CONSTRAINT UNPREDICTABLE behaviour (1 and 3): "If regs > 16 || (d+regs) > 32 , then one of the following behaviors must occur: 1) The instruction is UNDEFINED . 2) The instruction executes as NOP . 3) One or more of the SIMD and floating-point registers are UNKNOWN . If the instruction specifies writeback, the base register becomes UNKNOWN . This behavior does not affect any general-purpose registers." This patch unfies the behaviour by always opting for option 1) over 3) Change-Id: I4f98409243d5a2ec64113fe9c87e961a391abe94 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23106 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Fix NumVecV7ArchRegs value (64->16)Giacomo Travaglini
In armv7 there are 16 only quadword (vector) registers which are usable by SIMD instructions (Q0-Q15). Those completely overlap with the 32 double word registers (D0-D31). NumVecV7ArchRegs = 16; // Q0-Q15 Change-Id: Id8fee1064d60dcfa54f273fa7d579a20c0087835 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23105 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Reorder arch/arm/registers.hh constantsGiacomo Travaglini
This is putting some order in the constants definition, respecting the description which divides: * Constants Related to the number of registers (example: const int NumFloatRegs = 0) from: * Semantically meaningful register indices (to indicate special registers) (example: const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs) Change-Id: I1760b7f786b6f6becbe8ab445e65fc3fa17206cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23104 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegsGiacomo Travaglini
gem5-ARM is not using floatRegs anymore and moved towards the vecRegs register file (which is used for SIMD&FP + SVE instructions) Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-09mem: Add Request::isMasked to check for byte strobingGiacomo Travaglini
This is trying to overcome the following problem: At the moment a memory request with a non empty byteEnable mask will be considered masking even if all elements in the vector are true. Change-Id: I16ae2c0ea8c3f3370e397bab9d79d6d60c3784bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23284 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-09mem: Add byteEnable copy to Request copy constructorGiacomo Travaglini
Change-Id: Ie97543e62524bb244ae65eef096411af4605c175 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23283 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-08arch-riscv: set MaxMiscDestRegs to 2Alec Roelke
In an earlier patch, the FCSR was split into its two components, FRM and FFLAGS, causing explicit writes to FCSR to incur two CSR writes. With the O3 CPU model, which defers them both to later, this creates a bug where an assertion that the number of CSR writes must be less than MaxMiscDestRegs fails because that constant is 1. This patch sets it to 2 so the O3 CPU is compatible with this scheme. Change-Id: Ic3413738c4eebe9f127980d0d0af5033d18468e7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23220 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-07scons: Set the partial linking group for EXTRAS dirs.Gabe Black
Partial linking heuristically links together files in the same directory by setting a special automatic tag. That tag needs to also be maintained when scanning EXTRAS dirs so that they don't all get lumped in with the last normal directory that was processed. Change-Id: I2408ea0a1eeffcf6d9994c36415a35760b225b17 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23300 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-06kvm,arm: Update the KVM ARM v8 CPU to use vector regs.Gabe Black
The exact mapping of the KVM registers and the gem5 registers is direct and may not actually be correct. Change-Id: Idb0981105c002e65755f8dfc315dbb95ea9370df Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23402 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-05arch-x86: missing override specifierAndrea Mondelli
Change-Id: I5a6db4632ec5b670cbfeb7d52190a7545c0b985f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23380 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-05arch-x86: Adding LDDQU instructionmarjanfariborz
Tested with simple c binaries. Signed-off-by: marjanfariborz <mfariborz@ucdavis.edu> Change-Id: I2f0852b136f966381d29af523e8ffdbca795afcd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23262 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-04sim: Add a suppression mechanism to the SyscallReturn class.Gabe Black
It makes more sense to specify whether something should be returned based on the return, not intrinsically on the syscall. This is especially true in cases like execve where the expected behavior is not constant. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I95b53b6d69445c7a04c0049fbb0f439238d971e8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23166 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-04sim: Small style fixes in sim/syscall_return.hh.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I485004843393c2e10c1ff4dbd84fc30ca4fd490c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23165 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-04sim: Change the syscall executor to a std::function.Gabe Black
This will enable using other types of callable like a lambda. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: If9f7176205492830824b5fe3c00f2c7710f57f70 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23164 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-04sparc: Fix the getresuidFunc prototype.Gabe Black
When the syscall signature was changed to not take a Process pointer, the prototype for getresuidFunc was not updated. Change-Id: I887cc3e3aa8483fc608df9963876a0ac6fa2251d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23320 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-04sparc: Fix the predecoder's moreBytes method.Gabe Black
Endianness transformation was moved from the CPU into this method, making the "inst" parameter guest endian instead of host endian. The emi member of the decoder was set using the betoh method, ensuring that it was still stored in host order. Unfortunately, the "inst" parameter was used in some places when setting up the rest of emi. This change replaces those uses of inst with emi. Change-Id: I0c7f9a1833db4b64fc1a5015cf10f6ba3f7c26a0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23163 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03systemc: Purposefully *expose* bind in the initiator socket.Gabe Black
Apparently the base version of bind actually *is* supposed to be accessible, so expose it with using instead of hiding it. Change-Id: Ie762c35d6322e744696ed597189b7773ea68c3b7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23322 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03fastmodel: Switch the diagnostic pragmas to GCC from clang.Gabe Black
Clang can handle both, and GCC throws a fit if it sees pragmas for clang. Change-Id: Ie9f2789f45706223b11ed5acdf8b371de6e7ee24 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23321 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03cpu,sim-se: move error checks in syscall methodsBrandon Potter
There is a check on a global flag denoting that the simulator has been configured to run in fullsystem mode. The check is conducted at runtime during calls to syscall methods. The high-level models are checking the flag when the check could be conducted further down the call chain (nearer to the actual Process invocation). Moving the checks should result in less copy-pasta as new models are developed. It might be argued that the checks should stay in place since an error would detected earlier; that may be true, but the error would be the same and the simulation should fail in either case. This arrangement requires fewer lines of code. The changeset also changes the check into a fatal error instead of a panic since usage (in fs mode) should result in immediate corruption. Change-Id: If387e27f166ac1374f3fe8b7befe3546e69adba7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23240 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03systemc,fastmodel: Use the gem5_scons error and warning functions.Gabe Black
Use them in place of messing with termcap directly. Change-Id: I093efa95e6b6ea7af198dc1395dce05ca6d6575f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23263 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03systemc: Suppress a spurious clang warning in the systemc headers.Gabe Black
Change-Id: Ife2251d370133383debda9b0439cb84eca80978d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23126 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03systemc: Fix up some lingering Accellera specific code in TLM v1.Gabe Black
This was missed initially, but clang complained about it. Change-Id: Ie6d240447a74f96faf9da87bd2f1134c1d82be8e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23128 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-03base: add the FmtStackTrace debug optionCiro Santilli
If given, a stack trace is printed after every debug message. This helps to localize where debug messages are being called from, which is often the critical information needed to debug certain problems. Change-Id: I82b8990c0d286393d5bdab05f718be3e89eadc40 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22003 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03sim-se: Avoid function overloading for syscall implementationGiacomo Travaglini
This patch is aligning the readlink and access syscalls to the open one, which is not overloading the openFunc, but it is factoring the implementation into a openImpl, which is used by both open and openat. This is needed if passing them to std::function, whose constructor is not able to handle overloaded functions. Change-Id: I50a8aacdfd675181b6fe9a2696220ee29cc5bc4b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23260 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03systemc: Add a bunch of missing overrides to the systemc headers.Gabe Black
Change-Id: I664d7b5e7c3b4dd6128d261c95fabaa3d1a97d88 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23125 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03fastmodel: Suppress a spurious warning on clang for amba_pv.h.Gabe Black
This header comes from the fast model distribution and so we can't (easily) disable the warning locally. Change-Id: I2c1eee48f8970bb17466f0759f0077a5d45e76af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23123 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-01arch-riscv: Fix disassembling of immediate for c.lui instructionIan Jiang
For compressed instruction c.lui, the 6-bit immediate is left-shifted by 12 bits in decoding. While the original Gem5 gives the left-shifted value directly in disassembly. This patch fixes the problem by adding a new template CILuiExecute to resume the immediate before outputting it in disassembly. Note: The immediate is sign-extended to 20-bit to be compatible with GCC. Change-Id: If73f72d3e8f85a8b10ce7a323379d8ad6c4c3085 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22567 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28dev-arm: Automatically assign PCI device ids in attachPciDeviceCiro Santilli
Simulation scripts currently need to assign PCI device addresses when adding new devices. This change moves this responsibility to the VExpress_GEM5_BASE::attachPciDevice method. Change-Id: I6d62af8a8f9176d964cc011dd8fb9744154bbb87 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22830 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-28dev-arm: device name in AmbaFake accessesAdrian Herrera
This patch prints the name of the AmbaFake device being accessed. This is useful for identifying the device triggering the warning. Change-Id: I69ca06d5d9bce73d918b8c8b46bb43e92597933b Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22847 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28mem-cache: Avoid hiding a virtual method in the dictionary compressor.Gabe Black
The non-virtual version is later used in overrides of the virtual version whcih takes more arguments. Change-Id: I102d1185c7a616337c2a0429daa998706189292f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23127 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28mem-cache: Remove a std::move clang says is unnecessary.Gabe Black
It also says it prevents an optimization. Change-Id: I9c21dc1a0c53cf70cefd1400564de07d1e845a75 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23124 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28arm: Make sure not to shift off of the end of a uint32_t in KVM.Gabe Black
The methods which set or get an attribute from the virtual GIC use a shift constant which is 32, but they store their result in a 32 bit variable and, according to clang, are used to shift 32 bit inputs. This is undefined behavior in terms of the shift, and will truncate off the value regardless. Change-Id: Ie9543ab9e6e1d5f86317a9210d220928b23ffaf8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23129 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-27base, python: Allow dirname selection for the interpreterGiacomo Travaglini
This is the second step towards being able to run dynamically linked applications when the guest ISA != than host ISA. Once the guest interpreter is loaded to memory, we are able to redirect shared object loads through the redirectPath interface. How do we load the guest interpreter? The elf file is for example asking for the /lib/ld-linux-aarch64.so interpreter. That would point to a valid dynamic linker/loader if guest ISA == host ISA, but if we are running on X86 we should point to the guest (aarch64 in the example) toolchain wherever it is installed. This patch is adding the --interp-dir option to point to the parent folder of the guest /lib in the host fs. Change-Id: Id27b97c060008d2e847776a49323d45c8809a27f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23066 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-27base: Fix DPRINTF_UNCONDITIONAL on gem5.fastGiacomo Travaglini
Change-Id: I1e559f9c5daae1e9af307cd352791c1b1ac9bbdb Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23108 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-27sim-se: Check Path redirection when mmappingGiacomo Travaglini
Every syscall file access should go through the redirection process Change-Id: I1ba2063b5a254e11f47392bdad0bf0887ba73d3d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23063 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26sim: prefix --debug-flags Event logs with the flag nameCiro Santilli
Sample output of FmtFlag,ExecAll,Event: 0: Event: Event_70: generic event rescheduled @ 18446744073709551615 0: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue 0: Event: AtomicSimpleCPU tick.wrapped_function_event 500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+4 500: Event: AtomicSimpleCPU tick.wrapped_function_event 1000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+8 1000: Event: AtomicSimpleCPU tick.wrapped_function_event 1500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+12 1500: Event: AtomicSimpleCPU tick.wrapped_function_event Change-Id: I7f252b57d7778a15a3dda40d909bdb4425557a40 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22009 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-06 05:48:47 +0000