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2019-02-08kern,sim: implement FUTEX_WAKE_OPMoyang Wang
This patch implements FUTEX_WAKE_OP operation in the futex syscall. Below is its description: int futex(int *uaddr, int futex_op, int val, const struct timespec *timeout, int *uaddr2, int val3); This operation was added to support some user-space use cases where more than one futex must be handled at the same time. The most notable example is the implementation of pthread_cond_signal(3), which requires operations on two futexes, the one used to implement the mutex and the one used in the implementation of the wait queue associated with the condition variable. FUTEX_WAKE_OP allows such cases to be implemented without leading to high rates of contention and context switching. Reference: http://man7.org/linux/man-pages/man2/futex.2.html Change-Id: I215f3c2a7bdc6374e5dfe06ee721c76933a10f2d Reviewed-on: https://gem5-review.googlesource.com/c/9630 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08sim, kern: support FUTEX_CMP_REQUEUEMoyang Wang
This patch supports FUTEX_CMP_REQUEUE operation. Below is its description from Linux man page: futex syscall: int futex(int *uaddr, int futex_op, int val, const struct timespec *timeout, int *uaddr2, int val3); This operation first checks whether the location uaddr still contains the value val3. If not, the operation fails with the error EAGAIN. Otherwise, the operation wakes up a maximum of val waiters that are waiting on the futex at uaddr. If there are more than val waiters, then the remaining waiters are removed from the wait queue of the source futex at uaddr and added to the wait queue of the target futex at uaddr2. The val2 argument specifies an upper limit on the number of waiters that are requeued to the futex at uaddr2. Reference: http://man7.org/linux/man-pages/man2/futex.2.html Change-Id: I6d2ebd19a935b656d19d8342f7ab450c0d2031f4 Reviewed-on: https://gem5-review.googlesource.com/c/9629 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08sim: handle the case when there're not enough HW thread contextsTuan Ta
In SE mode, since there's no OS scheduler, the number of active SW threads is limited by the number of HW thread contexts. Previously, if there is no spare HW thread context, the simulator just fails and stops. Instead, this patch returns EAGAIN error code from a clone syscall if there's no available HW thread context. Then it's up to the simulated program to handle the error. Linux man page reference: http://man7.org/linux/man-pages/man2/clone.2.html http://man7.org/linux/man-pages/man2/fork.2.html Change-Id: Ib4e092433e49de4dde376c8cb81f7d3f7851cbc0 Reviewed-on: https://gem5-review.googlesource.com/c/9628 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08riscv: fixed syscall return valueTuan Ta
In case of failure, a syscall returns a negative value encoding the error code. This patch makes the risc-v implementation returns the encoded value instead of its absolute value upon a failure of a syscall. Change-Id: I6032b0337fe1cff5b326dbc6bb3b87a415f03300 Reviewed-on: https://gem5-review.googlesource.com/c/9627 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2019-02-08cpu: fix how branching is handled when a thread is suspended in MinorCPUTuan Ta
When a thread is suspended, all instructions after the suspension need to be discarded since the thread will take a different execution stream when it wakes up. To do that, in MinorCPU, whenever a thread gets suspended, we change the current execution stream by updating the current branch with BranchData::SuspendThread reason. Change-Id: I7cdcda22c1cf6e8ac8db8800b7d9ec052433fdf3 Reviewed-on: https://gem5-review.googlesource.com/c/9626 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08cpu: stop scheduling suspended threads in all stages of MinorCPUTuan Ta
This patch makes suspended threads non-schedulable in Fetch1, Fetch2, Decode and Execute stages in MinorCPU. Change-Id: Ie79857e13b7b782d9c58c32310993a132b609cf9 Reviewed-on: https://gem5-review.googlesource.com/c/9625 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08riscv: ignore nanosleep syscallTuan Ta
Change-Id: I564a09564da668a5db3e75f15b33efaca363d71a Reviewed-on: https://gem5-review.googlesource.com/c/9624 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08sim,cpu: make exit_group halt all threads in a groupTuan Ta
When a thread calls exit_group, in addition to halting the thread itself, it needs to halt all other threads in its group (i.e., threads sharing the same thread group ID). This patch enables threads to do that. Change-Id: Ib2e158fb27cf98843f177a64a2d643b1bbc94d03 Reviewed-on: https://gem5-review.googlesource.com/c/9623 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08arch-riscv: initialize RISC-V's thread pointer register in clone syscallTuan Ta
This patch initializes thread pointer register to Thread Local Storage (TLS)'s pointer given to a clone system call. Change-Id: I03e2cf4763e6a0ed31f357772a513a05e1e3461b Reviewed-on: https://gem5-review.googlesource.com/c/9622 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET opsTuan Ta
This patch adds support for two operations in futex system call: FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET. The two operations are used to selectively wake up a certain thread waiting on a futex variable. Basically each thread waiting on a futex variable is associated with a bitset that is checked when another thread tries to wake up all threads waiting on the futex variable. Change-Id: I2300e53b144d8fae226423fa2efb0238c1d93ef9 Reviewed-on: https://gem5-review.googlesource.com/c/9621 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
When a thread executed an exit syscall in SE mode, the thread context was removed immediately in the same cycle, which left inflight squash operations and trap event incomplete. The problem happened when a new thread was assigned to the CPU later. The new thread started with some incomplete transactions of the previous thread (e.g., squashing). This problem could cause incorrect execution flow for the new thread (i.e., pc was not reset properly at the exit point), deadlock (i.e., some stage-to-stage signals were not reset) and incorrect rename map between logical and physical registers. This patch adds a new state called 'Halting' to the thread context and defers removing thread context from a CPU until a trap event initiated by an exit syscall execution is processed. This patch also makes sure that the removal of a thread context happens after all inflight transactions of the to-be-removed thread in the pipeline complete. Change-Id: If7ef1462fb8864e22b45371ee7ae67e2a5ad38b8 Reviewed-on: https://gem5-review.googlesource.com/c/8184 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08arch-arm: Fix Virtual interrupts in AArch64Giacomo Travaglini
Checking if cpsr.mode is equal to MODE_HYP doesn't work for AArch64. This is because AArch64 is using different modes when in EL2, like EL2T and EL2H. This made Virtual Interrupts to be triggered even when executing in EL2 (hypervisor) whereas they should interrupt the scheduled VM only (Non-Secure EL0 and EL1). This patch is fixing this by using the generic currEL() helper for getting the exception level, which is working for both AArch32 and AArch64. Change-Id: I08640050ef06261f280ba1e63ca9f32c805af845 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16202 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-08arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30Giacomo Travaglini
Change-Id: I649f8507ccb6c814b46b0b9b7e39dc912ecd9006 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16242
2019-02-08arch-arm: Allow ArmPPI usage for PMUGiacomo Travaglini
Differently from ArmSPIs, ArmPPI interrupts need to be instantiated by giving a ThreadContext pointer in the ArmPPIGen::get() method. Since the PMU is registering the ThreadContext only at ISA startup time, ArmPPI generation in deferred until the PMU has a non NULL pointer. Change-Id: I17daa6f0e355363b8778d707b440cab9f75aaea2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16204 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-08arch-arm: Fix initialization of PMU countersRuben Ayrapetyan
A version of Linux kernel initializes counters before enabling them. Without this change, gem5 overwrites the value of counter, which causes incorrect counter values derived by kernel. Change-Id: If0c515111103018d5f65f74434d7711a67aeaee4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16203 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
Physical memory ranges are now saved in Realview objects as pairs of addresses (start address and size). This patch is substituting them with a single AddrRange object. Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16206 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-07arch-riscv: Enable support for riscv 32-bit in SE mode.Austin Harris
This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-02-06riscv: remove NonSpeculative flag from fence instTuan Ta
Fence instruction origially had two flags NonSpeculative and MemBarrier. In O3 model, MemBarrier instructions are inserted into the instruction queue by the InstructionQueue::insertBarrier (at src/cpu/o3/iew_impl.hh:1083). Barrier instructions are implicitly assumed to be non-speculative. Adding NonSpeculative flag to fence instruction makes it inserted into the instruction queue twice (at src/cpu/o3/iew_impl.hh:1083 and :1111). This can lead to a deadlock if both pointers to the instruction are not cleared from the queue when the instruction retires. This patch removes NonSpeculative flag from the fence inst. Change-Id: I26573d12a0b52f43b73c0e51158286dc98d05ea4 Reviewed-on: https://gem5-review.googlesource.com/c/8183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2019-02-06cpu: fix how a thread starts up in MinorCPUTuan Ta
When a thread is activated by another thread calling a clone system call, the child thread's context is initialized in the middle of the clone system call and before the context is fully initialized. Therefore, the child thread starts fetching an unitialized PC, which could lead to a page fault. This patch adds a pipeline wakeup event that is scheduled later in the cycle when the thread is activated. This event ensures that the first fetch only happens after the thread context is fully initialized (e.g., in case of clone syscall, it is when the parent thread copies its context over to the child thread). When a thread first starts or wakes up, input queue to the Fetch2 stage needs to be drained since the execution flow is likely to change and previously fetched instructions in the queue may no longer be in the correct flow. This patch dumps/drains all inputs in the input queue of a thread context in the Fetch2 stage when the associated thread wakes up. Change-Id: Iad970638e435858b7289cd471158cc0afdbbb0e5 Reviewed-on: https://gem5-review.googlesource.com/c/8182 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-06arch-riscv: Initialize interrupt maskTuan Ta
This patch initializes RISCV interrupt mask to 0. Change-Id: I56289d9f3f319e239e305befea006a0ad4d86b75 Reviewed-on: https://gem5-review.googlesource.com/c/16162 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-06scons: fix unused auto-generated blob variable in clangCiro Santilli
Since f2bda876f73af4ecc38406f3562a3d16fd28a5a9, the build system started adding a length for generated blobs as in: const std::size_t variable_len = 123; There were two types of blob files, ones with a header and the ones without. The ones with the header, also include the header in the .cc of the blob, which contains a declaration: extern const std::size_t variable_len; Therefore, the ones without header, don't have that extern declaration, which makes them static according to the C++ standard. clang then correctly interprets that as problematic due to -Wunused-const-variable, while GCC does not notice this. This patch removes the length declaration from the blob files that don't have the header. Those files currently don't use the length. Change-Id: I3fc61b28f887fc1015288857328ead2f3b34c6e6 Reviewed-on: https://gem5-review.googlesource.com/c/15955 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-06sim: added missed macro definition on MacOSAndrea Mondelli
A recent patch add the use of the macro: CMSG_ALIGN This macro is not very cross-platform, and needs to be defined according to the platform. This patch defines the missing macro on MacOS. Change-Id: I582f69e652dc060b4532358141179ad6d37eafc7 Reviewed-on: https://gem5-review.googlesource.com/c/16102 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-05misc: added missing override specifierAndrea Mondelli
Added missing specifier for various virtual functions. Change-Id: I4783e92d78789a9ae182fad79aadceafb00b2458 Reviewed-on: https://gem5-review.googlesource.com/c/16103 Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-05cpu: Made the Loop Predictor a SimObjectJavier Bueno
The Loop Predictor implementation is now a SimObject so that other branch predictors can easily use it (including LTAGE, which is now using it). It has also been updated with the latest available loop predictor implementation from Andre Seznec: http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 Reviewed-on: https://gem5-review.googlesource.com/c/15775 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-05cpu: Made TAGE a SimObject that can be used by other predictorsJairo Balart
The TAGE implementation is now a SimObject so that other branch predictors can easily use it. It has also been updated with the latest available TAGE implementation from Andre Seznec: http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar Change-Id: I2251b8b2d7f94124f9955f52b917dc3b064f090e Reviewed-on: https://gem5-review.googlesource.com/c/15317 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-05riscv: Get rid of ISA specific register types in Interrupts.Austin Harris
Change-Id: I5542649c6af27a286f276a289b86c40dd7e32abc Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/16122 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-01mem-cache: Updated version of the Signature Path PrefetcherJavier Bueno
This implementation is based in the description available in: Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, and Zeshan Chishti. 2016. Path confidence based lookahead prefetching. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 60, 12 pages. Change-Id: I4b8b54efef48ced7044bd535de9a69bca68d47d9 Reviewed-on: https://gem5-review.googlesource.com/c/14819 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-01dev, arm: Removed contextId variableAnouk Van Laer
The contextId variable is only used by the debug flag and will prevent a more optimised binary (i.e. fast) from compiling. Change-Id: I6cefb5bc06d0d4b415df62f1278db53ba309fb87 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16042 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
Most architectures weren't using the CCReg type, and in x86 and arm it was already a uint64_t. Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6 Reviewed-on: https://gem5-review.googlesource.com/c/14515 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31python: Remove getCode() type workaroundAndreas Sandberg
Python 2.7 requires a workaround when wrapping exit objects to explicitly convert the return of getCode() to int to not confuse sys.exit. This workaround isn't needed and doesn't work on Python 3 since it doesn't have a separate long integer type. Change-Id: I57bc3fd8f4699676c046ece8a52baa2796959ffd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15978 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-31sim: Prepare C++ side for Python 3Andreas Sandberg
Python 3 uses wide strings instead of ordinary strings for many APIs. Add the necessary conversions to comply with the new API. Change-Id: I6f45c9c532537d50d54b542f34eb8fd8cb375874 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15977 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-31power: Get rid of some ISA specific register types.Gabe Black
Change-Id: If63acb10705a9f442255680917d16630748ca8e1 Reviewed-on: https://gem5-review.googlesource.com/c/14465 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31null: Get rid of some register type definitions.Gabe Black
These are no longer used. Change-Id: Ic6a35e8a7e25eab9d21a3eef683914e01508c6d7 Reviewed-on: https://gem5-review.googlesource.com/c/14463 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31mips: Stop using architecture specific register types.Gabe Black
Change-Id: I764f6eea214ba4e03cc0fe19a21abcb0ebd04408 Reviewed-on: https://gem5-review.googlesource.com/c/14462 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31alpha: Stop using architecture specific register types.Gabe Black
Change-Id: I4052000014c9f6f9ecefd3f37e58595c61599484 Reviewed-on: https://gem5-review.googlesource.com/c/14461 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31x86: Stop using/defining some ISA specific register types.Gabe Black
These have been replaced with the generic RegVal type. Change-Id: I75c1134212067dea43aa0903d813633e06f3d6c6 Reviewed-on: https://gem5-review.googlesource.com/c/14476 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31riscv: Get rid of some ISA specific register types.Gabe Black
Change-Id: Ie812cf1d42536094273ba2ec731c16cca38db100 Reviewed-on: https://gem5-review.googlesource.com/c/14466 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
Now that there's no plain FloatReg, there's no reason to distinguish FloatRegBits with a special suffix since it's the only way to read or write FP registers. Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded Reviewed-on: https://gem5-review.googlesource.com/c/14460 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector Extension (SVE), introduce the notion of a predicate register file. This changeset adds this feature across architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13715 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-30arch-arm, configs: Create single instance of DTB autogenerationGiacomo Travaglini
This patch is rewriting the DTB autogeneration functions available in fs_bigLITTLE.py and fs.py as a single method in the GenericArmSystem so that other configuration scripts can make use of it. Change-Id: I492bbf77e6b0ac5c5fbdbc75c0eecba29bd63bda Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15958 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Remove floatReg operand typeGiacomo Travaglini
Change-Id: I87553257ce9c42d0e2514d5a1f010bc6e2e7f21e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15604 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Use VecElem instead of FloatReg for FP instructionGiacomo Travaglini
SIMD & FP Operations use FloatRegs in AArch32 mode and VecRegs in AArch64 mode. The usage of two different register pools breaks interprocessing between A32 and A64. This patch is changing definition of arm operands so that they are backed by VecElems in A32, which are mapped to the same storage as A64 VecRegs. Change-Id: I54e2ea0ef1ae61d29aca57ab09acb589d82c1217 Reviewed-on: https://gem5-review.googlesource.com/c/15603 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch: Fix VecElem Operand generation in ISA parserGiacomo Travaglini
Fixes include: * Change of reg_class: VecElemClass in lieau of non-existing VectorElemClass. * Removal of unused regId in operand constructor * makeRead and makeWrite are using VecElem (which is a typedef of uint32_t) as a source/destination type, regardless of the real operand type (which is specified by ctype) Change-Id: I4588e1120e1fc8fdb68b2b2f05d5e3692c55b2e8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15602 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601
2019-01-25cpu: O3 rename using the flatIndex instead of indexGiacomo Travaglini
This patch is replacing the RegId::index with RegId::flatIndex so that it provides a valid register number when used by a VecElem register. Change-Id: I5b000abb9457cd325c2a3021e772a75ea33d8a4c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15600 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Inital vector rename mode depending on A32/A64Giacomo Travaglini
Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481 Reviewed-on: https://gem5-review.googlesource.com/c/15599 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25cpu: Fix VecElemClass bugs in cpu modelsGiacomo Travaglini
This patch is: * Adding a missing VecElemClass entry * Fixing assertion in rename map which was checking the number of free vector registers rather than free vector element registers * Fixing assertion in read/setVecElemOperand APIs. * Using the right register index in SimpleThread * Using VecElem instead of VecReg on O3 readArchVecElem Change-Id: I265320dcbe35eb47075991301dfc99333c5190c4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15598 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25cpu: Add VecElem entries in MinorCPU ScoreboardGiacomo Travaglini
This patch is: * Increasing the number of bits in the Scoreboard so that it is keeping track of VecElemClass dependencies. * Fixing VecElemClass entry in the scoreboard table so that it correctly uses flatIndex rather than index. Change-Id: Ie4877e5fe410b1437447adebbe289602a443f7c0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15597 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Remove unused float operandsGiacomo Travaglini
Removing FaP1 and FDest2 since they are not currently used by any ARM instruction. Change-Id: I4251dfcdd3f4434caaf0bdab507c1c3bd53fb5d2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15596 Reviewed-by: Ciro Santilli <ciro.santilli@gmail.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch: Provide traceback when parsing ISA codeGiacomo Travaglini
There is no line information When the ISA code is executed inside the isa_parser environment and an error is encountered. The build stops and reports the line of the let block containing the error. This patch is enhacing the error reporting by printing the traceback of the faulting ISA code. Change-Id: I3acd17f0d78b2feb8fe6e48808a094c5b81624e6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15595 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-26 18:09:25 +0000