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2017-04-03arm, kvm: implement GIC state transferCurtis Dunham
This also allows checkpointing of a Kvm GIC via the Pl390 model. Change-Id: Ic85d81cfefad630617491b732398f5e6a5f34c0b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2444 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, dev: add basic support for GICC_BPR registerCurtis Dunham
The Binary Point Register (BPR) specifies which bits belong to the group priority field (which are used for preemption) and which to the subpriority field (which are ignored for preemption). Change-Id: If51e669d23b49047b69b82ab363dd01a936cc93b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2443 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handlingCurtis Dunham
The aforementioned registers (Interrupt Processor Targets Registers) are banked per-CPU, but are read-only. This patch eliminates the per-CPU storage of these values that are simply computed. Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2442 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: refactor packet processing in Pl390 GICCurtis Dunham
Change-Id: I696703418506522ba90df5c2c4ca45c95a6efbea Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2441 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: Don't panic when checking coprocessor read/write permissionsNikos Nikoleris
Instructions that use the coprocessor interface check the current program status to determine whether the current context has the priviledges to read from/write to the coprocessor. Some modes allow the execution of coprocessor instructions, some others do not allow it, while some other modes are unexpected (e.g., executing an AArch32 instruction while being in an AArch64 mode). Previously we would unconditionally trigger a panic if we were in an unexpected mode. This change removes the panic and replaces it with an Undefined Instruction fault that triggers if and when a coprocessor instruction commits in an unexpected mode. This allows speculative coprocessor instructions from unexpected modes to execute but prevents them from gettting committed. Change-Id: If2776d5bae2471cdbaf76d0e1ae655f501bfbf01 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2281 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: Treat Write-Through Normal memory as Non-CacheableNikos Nikoleris
A completed write to a memory location that is Write-Through Cacheable has to be visible to an external observer without the need of explicit cache maintenance. This change adds support for Write-Through Cacheable Normal memory and treats it as Non-cacheable. This incurs a small penalty as accesses to the memory do not fill in the cache but does not violate the properties of the memory type. Change-Id: Iee17ef9d952a550be9ad660b1e60e9f6c4ef2c2d Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2280 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03sim: Handle cases where Drainable::resume() creates objectsAndreas Sandberg
There are cases where Drainable objects need to create new objects in Drainable::resume(). In such cases, the local drain state will be inherited from the DrainManager. We currently set the state to Running as soon as we start resuming the simulator. This means that new objects are created in the Running state rather than the Drained state, which the resume code assumes. Depending on the traversal order in DrainManager::resume(), this sometimes triggers a panic because the object being resumed is in the wrong state. This change introduces a new drain state, Resuming, that the DrainManager enters as soon as it starts resuming the simulator. Objects that are created while resuming are created in this state. Such objects are then resumed in a subsequent pass over the list of Drainable objects that need to be resumed. Once all objects have been resumed, the simulator enters the Running state. Change-Id: Ieee8645351ffbdec477e9cd2ff86fc795e459617 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2600 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, kvm: Override the kernel's default MPIDR valueAndreas Sandberg
The kernel and gem5 derive MPIDR values from CPU IDs in slightly different ways. This means that guests running in a multi-CPU setup sometimes fail to bring up secondary CPUs. Fix this by overriding the MPIDR value in virtual CPUs just after they have been instantiated. Change-Id: I916d44978a9c855ab89c80a083af45b0cea6edac Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2461 Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03dev, arm: Fix multi-core KVM race in the generic timerAndreas Sandberg
The generic timer sometimes needs to access global state. This can lead to race conditions when simulating a multi-core KVM system where each core lives in its own thread. In that case, the setMiscReg and readMiscReg methods are called from the thread owning the CPU and not the global device thread. Change-Id: Ie3e982258648c8562cce0b30a0c122dfbfaf42cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2460 Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03dev: Align BAR0 size to power of 2 for VirtIO devicesSascha Bischoff
When setting the size of a PCI BAR, the kernel only supports powers of two (as per the PCI spec). Previously, the size was incorrectly read by the kernel, and the address ranges assigned to the PCI devices could overlap, resulting in gem5 crashes. We now round up to the next power of two. Kudos to Sergei Trofimov who helped to debug this issue! Change-Id: I54ca399b62ea07c09d4cd989b17dfa670e841bbe Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-by: Sergei Trofimov <sergei.trofimov@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2580 Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
2017-04-03dev: Add a dummy VirtIO deviceAndreas Sandberg
VirtIO transport interfaces always expect a VirtIO device pointer. However, there are cases (in particular when using VirtIO's MMIO interface) where we want to instantiate an interface without a device. Add a dummy device using VirtIO device ID 0 and no queues to handle this use case. Change-Id: I6cbe12fd403903ef585be40279c3b1321fde48ff Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2325 Reviewed-by: Weiping Liao <weipingliao@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03dev: Rename VirtIO PCI debug flagAndreas Sandberg
Rename VIOPci -> VIOIface to avoid having a separate flag for the MMIO interface. Change-Id: I99f9210fa36ce33662c48537fd3992cd9a69d349 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2324 Reviewed-by: Weiping Liao <weipingliao@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03arm: fix template instantiation warning in clangMatteo Andreozzi
In arch/arm/faults.hh, template the static member vals require explicit specialisation to avoid compiler warnings. Change-Id: Ie404ccaa43269cb1bb819e33153e776abbf3a79b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-21arm: correct register read bug in Pl390 GICCurtis Dunham
Change-Id: I4c0de7c2a5b40c1a9f009ca12062cb108b450b04 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-21python: Automatically disable listeners in batch setupsAndreas Sandberg
Determine if gem5 is running in a batch environment by checking if STDIN is wired to a TTY or not. If the simulator is running in a batch environment, disable all listeners by default. This behavior can be overridden using the --enable-listeners option. Change-Id: I404c709135339144216bf08a2769c016c543333c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sean McGoogan <sean.mcgoogan@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2322 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-17syscall-emul: Hotfix for FreeBSD/Mac buildsBrandon Potter
The clone system call added in 236719892 relies on header files from Linux systems. Obviously, this prevents compilation for anyone using FreeBSD or Mac to compile the simulator. This changeset is meant as a temporary fix to allow builds on non-Linux systems until a proper solution is found. Change-Id: I404cc41c588ed193dd2c1ca0c1aea35b0786fe4e Reviewed-on: https://gem5-review.googlesource.com/2420 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-17syscall-emul: change NULL to nullptr in Process filesBrandon Potter
Change-Id: I9ff21092876593237f919e9f7fb7283bd865ba2e Reviewed-on: https://gem5-review.googlesource.com/2421 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-03-16cpu: Print progress messages in Trace CPURadhika Jagtap
This change adds the ability to print a message at intervals of committed instruction count to indicate progress in the trace replay. Change-Id: I8363502354c42bfc52936d2627986598b63a5797 Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2321 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-15arm, dev: Add missing override in the Pl390 GIC modelAndreas Sandberg
The Pl390::getAddrRanges() method should have been flagged using the override keyword. Other methods in this class already use the override keyword, so this results in a warning about inconsistent override usage when compiling using clang. Change-Id: I17449687a8e074262232562487b58c96466bd54e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-13dev, arm: Add draining to the GIC modelAndreas Sandberg
The GIC model currently adds a delay to interrupts when posting them to a target CPU. This means that an interrupt signal will be represented by an event for a short period of time. We currently ignore this when draining and serialize the tick when the interrupt will fire. Upon loading the checkpoint, the simulated GIC reschedules the pending events. This behaviour is undesirable when we implement support for switching between in-kernel GIC emulation and gem5 GIC emulation. In that case, the (kernel) GIC model gets a lot simpler if we don't need to worry about in-flight interrupts from the gem5 GIC. This changeset adds a draining check to force the GIC into a state where all interrupts have been delivered prior to checkpointing/CPU switching. It also removes the now redundant serialization of interrupt events. Change-Id: I8b8b080aa291ca029a3a7bdd1777f1fcd5b01179 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2331 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-13arm: Clean up the GIC implementationAndreas Sandberg
Lots of minor cleaups: * Make cached params const * Don't serialize params * Use AddrRange to represent the distributor and CPU address spaces * Store a const AddrRangeList of all PIO ranges Change-Id: I40a17bc3a38868fb3b8af247790e852cf99ddf1d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2330 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-09style: change NULL to nullptr in syscall filesBrandon Potter
Change-Id: I02719f3572f6665cace1eb5681f297dcde9e71ce Reviewed-on: https://gem5-review.googlesource.com/2271 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-09syscall-emul: Ignore unimplemented system callsBrandon Potter
This changeset sets the implementation policy for a subset of system calls to the ignoreFunc implementation (for x86 only). The ignored system calls likely will never be implemented and this allows a warning to be issued instead of the simulation exiting with a fatal. Change-Id: I8d9741ad683151e88cc71156d3602e2d0ccb0acf Reviewed-on: https://gem5-review.googlesource.com/2270 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-09syscall-emul: Rewrite system call exit codeBrandon Potter
The changeset does a major refactor on the exit, exit_group, and futex system calls regarding exit functionality. A FutexMap class and related structures are added into a new file. This increases code clarity by encapsulating the futex operations and the futex state into an object. Several exit conditions were added to allow the simulator to end processes under certain conditions. Also, the simulation only exits now when all processes have finished executing. Change-Id: I1ee244caa9b5586fe7375e5b9b50fd3959b9655e Reviewed-on: https://gem5-review.googlesource.com/2269 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-09syscall-emul: Add the tgkill system callBrandon Potter
This changeset adds support to kill a thread group by calling the tgkill system call. The functionality is needed in some pthread applications. Change-Id: I0413a3331be69b74dfab30de95384113ec4efb63 Reviewed-on: https://gem5-review.googlesource.com/2268 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
2017-03-09syscall-emul: Adds SE mode signal featureBrandon Potter
This changeset adds a simple class definition and a member in the System object to track signals sent between processes. The implementation cannot support all signals that might be sent between processes, but it can support some of the simple use cases like SIGCHLD. Change-Id: Id5f95aa60e7f49da1c5b5596fbfa26e729453ac7 Reviewed-on: https://gem5-review.googlesource.com/2267 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-09syscall-emul: Add or extend dup, dup2, and pipeBrandon Potter
This changeset extends the pipe system call to work with architectures other than Alpha (and enables the syscall for x86). For the dup system call, it sets the clone-on-exec flag by default. For the dup2 system call, the changeset adds an implementation (and enables it for x86). Change-Id: I00ddb416744ee7dd61a5cd02c4c3d97f30543878 Reviewed-on: https://gem5-review.googlesource.com/2266 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
2017-03-09syscall-emul: Add functionality to open syscallsBrandon Potter
This changeset adds refactors the existing open system call, adds the openat variant (enabled for x86 builds), and adds additional "special file" test cases for /proc/meminfo and /etc/passwd. Change-Id: I6f429db65bbf2a28ffa3fd12df518c2d0de49663 Reviewed-on: https://gem5-review.googlesource.com/2265 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
2017-03-09style: Correct some style issuesBrandon Potter
This changeset fixes line alignment issues, spacing, spelling, etc. for files that are used during SE Mode. Change-Id: Ie61b8d0eb4ebb5af554d72f1297808027833616e Reviewed-on: https://gem5-review.googlesource.com/2264 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
2017-03-09syscall-emul: Move memState into its own fileBrandon Potter
The Process class is full of implementation details and structures related to SE Mode. This changeset factors out an internal class from Process and moves it into a separate file. The purpose behind doing this is to clean up the code and make it a bit more modular. Change-Id: Ic6941a1657751e8d51d5b6b1dcc04f1195884280 Reviewed-on: https://gem5-review.googlesource.com/2263 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-09misc: add missing copyright/author information in previous commitPierre-Yves Péneau
See a06a46f and a854373. Change-Id: Id66427db22b7d7764c218b9cd78d95db929f4127 Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2224 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-09ruby: fix MOESI_hammer directory to work with > 3GB memoryLena Olson
The MOESI_hammer directory assumes a contiguous address space, but X86 has an IO gap from 3-4GB. This patch allows the directory to work with more than 3GB of memory on X86. Assumptions: the physical address space (range of possible physical addresses) is 0-XGB when X <= 3GB, and 0-(X+1)GB when X > 3GB. If there is no IO gap this patch should still work. Change-Id: I5453a09e953643cada2c096a91d339a3676f55ee Reviewed-on: https://gem5-review.googlesource.com/2169 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-07gpu-compute: Fix Python/C++ object hierarchy discrepanciesAndreas Sandberg
The GPUCoalescer and the Shader classes have different base classes in C++ and Python. This causes subtle bugs in SWIG and compilation errors for PyBind. Change-Id: I1ddd2a8ea43f083470538ddfea891347b21d14d8 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2228 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
2017-03-07power: Avoid forward declarations that confuse wrappersAndreas Sandberg
The Python wrappers get confused by the forward declarations in the power framework. This changeset restructures the code slightly to avoid the troublesome forward declarations. Change-Id: Id8c93224f1988edb5fdf9d3abc6237f2f688c02d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2227 Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-07dev, arm: Render HDLCD frames at a fixed rate in KVMSudhanshu Jha
Use the new fast scan-out API in the PixelPump to render frames at a fixed frame rate in KVM mode. The refresh rate when running in KVM can be controlled by the virt_refresh_rate parameter. Change-Id: Ib3c78f174e3f8f4ca8a9b723c4e5d311a433b8aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2242 Reviewed-by: Rahul Thakur <rjthakur@google.com>
2017-03-07dev: Add support for single-pass scan out in the PixelPumpSudhanshu Jha
Add a helper function to scan out an entire frame in one time step. This requires the public PixelPump to be changed somewhat to separate timing updates from general PixelPump control. Instead of calling PixelPump::start(timings), timings now need to be updated using a separate call to PixelPump::updateTimings(timings) before calling PixelPump::start(). Display controllers that don't need accurate timing (e.g., in KVM mode), can use the new PixelPump::renderFrame() API to render an entire frame in one step. This call results in the same callbacks (e.g., calls to nextPixel()) as the timing calls, but they all happen in immediately. Unlike the timing counterpart, renderFrame() doesn't support buffer underruns and will panic if nextPixle() indicates an underrun. Change-Id: I76c84db04249b02d4207c5281d82aa693d0881be Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2241 Reviewed-by: Rahul Thakur <rjthakur@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-07dev, kvm: Add a fast KVM-aware mode in DmaReadFifoSudhanshu Jha
Use a fast, functional, read operations keep the DMA FIFO full when running in KVM mode. Change-Id: I5b378c2fb6a1d3e687cef15e807e63a0a53a60e2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2226 Reviewed-by: Rahul Thakur <rjthakur@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-07arm, kmi: Clear interrupts in KMI devicesSudhanshu Jha
Added functionality to check and clear interrupts for KMI devices. This fixes a boot bug when using KVM and in-kernel GIC emulation. Change-Id: Ia3e91d07567b7faf3f82b0adfda4a165a502a339 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2225 Reviewed-by: Rahul Thakur <rjthakur@google.com>
2017-03-06syscall-emul: Remove unused class and memberBrandon Potter
The WaitRec structure in the Process class is unnecessary. There is a member declaration inside of the Process class, waitList, that uses the WaitRec definition. However, waitList is unused so they are both dead bits of code. This changeset removes both the WaitRec struct and waitList member from Process. Change-Id: Ia6ee7488b9f47fd0f0ae29c818fba6ea0710699c Reviewed-on: https://gem5-review.googlesource.com/2262 Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-03mem: Make blkAlign a common function between all tag classesNikos Nikoleris
blkAlign was defined as a separate function in the base associative and fully-associative tags classes although both functions implemented identical functionality. This patch moves the blkAlign in the base tags class. Change-Id: I3d415d0e62bddeec7ce0d559667e40a8c5fdc2d4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2017-03-03mem: Use pkt::getBlockAddr instead of BaseCace::blockAlignNikos Nikoleris
Change-Id: I0ed4e528cb750a323facdc811dde7f0ed1ff228e Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2017-03-03arm, kvm: enable running 32-bit Guest under ARM KVM64Rahul Thakur
1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit when running 32-bit OS 2) Correctly map 64-bit registers to banked 32-bit ones Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670 Reviewed-on: https://gem5-review.googlesource.com/2261 Maintainer: Rahul Thakur <rjthakur@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-03arm, kvm: fix saving/restoring conditional flags in ARM KVM64Rahul Thakur
The gem5 stores flags separately from other fields CPSR, so we need to split them out and recombine on trips to/from KVM. Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb Reviewed-on: https://gem5-review.googlesource.com/2260 Reviewed-by: Rahul Thakur <rjthakur@google.com> Maintainer: Rahul Thakur <rjthakur@google.com>
2017-03-01ruby: fix and/or precedence in sliccLena Olson
The slicc compiler currently treats && and || with the same precedence. This is highly non-intuitive to people used to C, and was probably an error. This patch makes && bind tighter than ||. For example, previously: if (A || B && C) compiled to: if ((A || B) && C) With this patch, it compiles to: if (A || (B && C)) Change-Id: Idbbd5b50cc86a8d6601045adc14a253284d7b791 Signed-off-by: Lena Olson (leolson@google.com) Reviewed-on: https://gem5-review.googlesource.com/2168 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Joe Gross <criusx@gmail.com> Reviewed-by: Sooraj Puthoor <puthoorsooraj@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> [ Rebased onto master ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-27syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess ↵Brandon Potter
simulations Modifies the clone system call and adds execve system call. Requires allowing processes to steal thread contexts from other processes in the same system object and the ability to detach pieces of process state (such as MemState) to allow dynamic sharing.
2017-02-27syscall_emul: [patch 14/22] adds identifier system callsBrandon Potter
This changeset add fields to the process object and adds the following three system calls: setpgid, gettid, getpid.
2017-02-27x86: remove unnecessary parameter from functionsBrandon Potter
2017-02-27gpu-compute: remove unnecessary member from classTony Gutierrez
The clang compiler complains that the wavefront member in the GpuISA class is unused. This changeset removes the member, because it does not appear serve a purpose.
2017-02-27gpu-compute: mark functions with override if replacing virtualBrandon Potter
The clang compiler is more stringent than the recent versions of GCC when dealing with overrides. This changeset adds the specifier to the methods which need it to silence the compiler.
2017-02-27arch: Include generated decoder header after normal headersAndreas Sandberg
The generated decoder header defines macros that represent bit fields within instructions. These fields typically have short names that conflict with names in other header files. Include the generated header after all normal header to avoid this issue. Change-Id: I53d149b75432c20abdbf651e32c3c785d897973b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 18:39:34 +0000