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2020-02-04arch-arm: reg access permissions highest EL helperAdrian Herrera
This patch implements a helper function to filter a register access permissions by the highest EL implemented by the system. This filtering is convenient to follow the architecture pseudocode. Change-Id: Iedfb2d8624c926f2f0a9326f8b1b073ea9424ab9 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24663 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-04arch-arm: Split translateFs to distinguish when MMU is on/offGiacomo Travaglini
This patch is splitting the big translateFs method so that it is using different methods when the MMU is on/off Change-Id: I198851bdbedf8a8e69730693ff87ffb9ed535ea3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24985 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01arch,sim: Merge initCPU into the ISA System classes.Gabe Black
Those classes are already ISA specific, so we can just move initCPU's contents there and take it out of utility.hh, utility.cc, and the base System's initState. Change-Id: I28f0d0b50d83efe5116b0b24d20f8182a02823e7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24905 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01arch,sim: Merge initCPU and startupCPU.Gabe Black
These two functions were called in exactly one place one right after the other, and served similar purposes. This change merges them together, and cleans them up slightly. It also removes checks for FullSystem, since those functions are only called in full system to begin with. Change-Id: I214f7d2d3f88960dccb5895c1241f61cd78716a8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24904 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01sim,cpu: Move the call to initCPU into System.Gabe Black
The call to initCPU was moved into initState in the base CPU class since it should only really be called when starting a simulation fresh. Otherwise checkpointed state will be loaded over the state of the CPU anyway, so there's no reason to set up anything else. Unfortunately that made it possible for the System level initialization and the CPU initialization to happen out of order, effectively letting initCPU clobber the state the System might have set up to prepare for executing a kernel for instance. To work around that issue, the call was moved to init which would necessarily happen before initState, restoring the original ordering. This change moves the change *back* into initState, but of the System class instead of the CPU class. This makes it possible to guarantee that OS initialization happens after initCPU since that's also done by System subclasses, and they control when they call initCPU of the base class. This also slightly simmplifies when initCPU is called since we shouldn't need to check whether a context is switched out or not. If it's registered with the System object, then it should be in a currently swapped in CPU. This also puts the initCPU and startupCPU calls right next to each other. A future change will take advantage of that and merge the calls together. Also, because there are already ISA specific subclasses of System which already have specialized versions of initState, we should be able to move the code in initCPU and startupCPU directly into those subclasses. That will give those subclasses more flexibilty if, for instance, they want all CPUs to start running in the BIOS like they would on a real system, or if they want only the BSP to be active as if the BIOS had already paused the APs before passing control to a bootloader or OS. This will also remove another two TheISA:: style functions, reducing the number of global dependencies on a single ISA. Change-Id: Ic56924660a5b575a07844a198f69a0e7fa212b52 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24903 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01arch,base,cpu: Add some default constructors/operators explicitly.Gabe Black
Having them implicitly is apparently deprecated and throws a warning in gcc 9, breaking the build. Change-Id: Id4e3074966d1ffc6dd1aed9397de5eea84400027 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24926 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01base: Delete an inet.hh accessor which is unused and makes gcc 9 upset.Gabe Black
This accessor will return a pointer to an unaligned uint32_t. Since it's not used and it's not clear how to fix it trivially, this change just deletes it. Change-Id: I08bc62276d639cc728411f3a8a23be385000ebab Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24925 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01scons: Disable spurious "array-bounds" warnings for protobuf cc files.Gabe Black
These files are generated and so, even if they're wrong, there isn't anything we can do about it. Change-Id: I933057a04f09dd1c22b525a102278bbdc5fbc22b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24924 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01scons: Add a mechanism to append flags when building particular files.Gabe Black
This could be used to tweak settings for a particular file if it needed special treatment. I plan to use this for protobuf files which generate code that produce a warning in gcc 9 which turns into an error. Change-Id: I53e2dac48cd68f0cc8ad9031d8484c5036d6e4a6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24923 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-31dev-arm: add boot_loader param to RealView setupBootLoaderCiro Santilli
This serves as a basis to select different bootloaders at runtime in future commits. Change-Id: I2ad0006fae9ad38ec1a6b1f11063be955a4dd2ea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23669 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-01-31mem: Make slicc generate some default methods explicitly.Gabe Black
Implicitly using the default copy constructor and assignment operator is apparently deprecated, and gcc 9 will warn about it, breaking the build. Change-Id: Ida7a8a577e9d1cde9841eac7eee1af74563f1e27 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24927 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Reviewed-by: John Alsop <johnathan.alsop@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2020-01-29cpu: move initCPU calls from initState to initAyaz Akram
This commit moves the initCPU calls from initState to init of base cpu (which were added in commit 0b8d02dec492215aa). This is a temporary fix to solve the problem of X86System initState getting called before initState of base cpu. Jira Issue: https://gem5.atlassian.net/browse/GEM5-292 Change-Id: I7434cd811536175562cfa2646f4326907fadad8c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24884 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-25sim: Add a GuestABI mechanism to allocate space for a return value.Gabe Black
Some ABIs (including 32 bit ARM, 64 bit x86) allocate their argument registers differently depending on their return value. For instance, if the value needs to be returned in memory because it's too big, the caller could pass a pointer to where the result should be stored when the function returns. This pointer acts like an invisible first argument, offsetting where all the normal arguments actually live. This change adds a mechanism to handle that case. The Result templates can now declare an allocate() static method which is given a ThreadContext *, and a reference to the Position object. It can perform any adjustment it needs to before the normal argument extraction starts. Change-Id: Ibda9095f0e8c9882742d24f5effe309ccb514188 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23747 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2020-01-23cpu: Fix ExeTraceRecord::traceInst.Gabe Black
A recent-ish change modified ExeTraceRecord::traceInst to make it more consistent with DPRINTF-s by using dprintf_flag to print the trace string. The generated string was passed as the format however, and that means that all % characters in the output (from register names, for example) are interpreted as format characters, mangling the output and making cprintf angry since there are no corresponding arguments. This change sets the format to "%s" instead, and passes the trace string as the first argument. The argument won't be parsed for format specifiers, and so should no longer get mangled. Change-Id: I8fa9c2c22179a5b55104a618a4af4080a3931c5f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24643 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-23sim: Move findFreeContext to System.Gabe Black
This method searches through the ThreadContexts stored in the system, and has no concrete connection to Process other than it happened to be used by a Process in the clone system call. By moving it, we can use its functionality in classes other than Process. Change-Id: Ic6899c335dc13841c6fe948ea3a4f8ad67e562bb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24285 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-23sim: Eliminate the breakAtKernelFunction function.Gabe Black
It looks like this function is supposed to allow you to set up a PC based event which will trigger when the simulator executes a particular kernel function. That event doesn't actually do anything, but you can set a breakpoint there with gdb when debugging gem5 itself. There are a couple of problems with this function. First, it assumes that you want to set the breakpoint based on the first system in your simulation. Frequently simulations have only one system, but there isn't any rule that says they must, or any way to pick a different system. Second, this function assumes that you're in FS mode, that there is a kernel, and that there is a kernel symbol table to look symbols up in. On top of that, this function is a bit redundant since you can just use gdb to debug the kernel inside a simulated system. Change-Id: I8dadbd42fc7d4ccba2a035a2a72e6ede4b872f3c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24644 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-23dev-arm: SP805 peripherals in VExpress_GEM5_BaseAdrian Herrera
This patch adds the SP805 watchdog peripherals to the VExpress_GEM5_Base platform. Change-Id: I5c597d4d169359c1bde4bc4c7b3403091c772808 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24206 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-01-23cpu: Consolidate and move the CPU's calls to TheISA::initCPU.Gabe Black
TheISA::initCPU is basically an ISA specific implementation of reset logic on architectural state. As such, it only needs to be called if we're not going to load a checkpoint, ie in initState. Also, since the implementation was the same across all CPUs, this change collapses all the individual implementations down into the base CPU class. Change-Id: Id68133fd7f31619c90bf7b3aad35ae20871acaa4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24189 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2020-01-22dev-arm: add Watchdog Module SP805 modelAdrian Herrera
This provides a model of the Arm Watchdog Module SP805. This is based on the public TRM rev. r1p0 (ARM DDI 0270B). Integration test harness is not supported. Auto-generation of device tree entries is provided. Change-Id: I6157cec2212d0a1d2685bcfa983d2acbae1f3377 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24205 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22dev-arm: VExpress_GEM5_Base, add refclock 32KHzAdrian Herrera
This patch adds the reference 32KHz clock to VExpress_GEM5_Base derived platforms. This is in preparation for supporting the SP805 Watchdog. I/O voltage domain and platform clock domain coupling is transferred to the __init__ method for correctness. Change-Id: Ic743fd986793f1e43b75fa60260c9b43b2737763 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24204 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22fastmodel: Implement CC reg accessors.Gabe Black
Change-Id: I4d8a7eaa097446b6aa3483880c2a7ed1a2e0d97c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23790 Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22arm: Remove checkpointing from the ARM TLBs.Gabe Black
All of the state being checkpointed would either be provided by the config directly, or would be brought into the TLB through normal fill operations. Having this state in the checkpoint complicates the checkpoint and significantly decreases compatibility with other TLB implementations, or even variations of the same TLB, for instance if the size was changed. Change-Id: I4ea079dd01ff18fbc458b3aaaf88519dbcfdd869 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24389 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22arch: Get rid of the unused (and mostly undefined) zeroRegisters.Gabe Black
Change-Id: Iadf56e4e742506af7ae4b617d2dc5a56439aa407 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24188 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-21dev-arm: add FixedClock SimObjectAdrian Herrera
This patch adds a simple fixed-rate clock implementation based on SrcClockDomain. This provides RealView-derived platform users with a convenient way for auto-generating their platform clocks in the DTB. Change-Id: Ifade0cc8ed1b9e3423745698442cac5d8b99ab63 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24223 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-21mem-cache: Fix invalidation of prefetchersDaniel R. Carvalho
Add an invalidation function to the AssociativeSet, so that entries can be properly invalidated by also invalidating their replacement data. Both setInvalid and reset have been merged into invalidate to indicate users that they are using an incorrect approach by generating compilation errors, and to match CacheBlk's naming convention. Change-Id: I568076a3b5adda8b1311d9498b086c0dab457a14 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24529 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-20arch-arm: Fix EL2 target exception level for SP alignment fault.Jordi Vaquero
This commit fixes the target exception Level EL2 for alignmemt fault, it is based on HCR_EL2.tge bit. Change-Id: Ief78b2aa0c86f1c3d9a5d3ca00121d163a9d6a86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24303 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-17mem-cache: Add print function to ReplaceableEntryDaniel R. Carvalho
Add a basic print function to acquire and display information about replaceable entries. Change-Id: I9640113d305fbe086c5bfaf8928a911bfcac50bb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23567 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2020-01-17mem-cache: Add getter for the number of valid sub-blksDaniel R. Carvalho
Add a getter function so that the number of valid sub-blocks can be retrieved. As a side effect, make the respective counter private. Change-Id: Icef8b51164c8e165872dcaebc65f5c330f16cb29 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22605 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-17mem-cache: Add multiple eviction statsDaniel R. Carvalho
Add stats to inform how many blocks were evicted due to a sector replacement/eviction. Change-Id: I886365506016d0888f835d182b3b65a808a9dccd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22606 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-17mem-cache: Make findVictim non-constDaniel R. Carvalho
In order to acquire stats when a victim is found, findVictim must be made const. Change-Id: I493c7849f07625c90b2b95fd220f50751f4d0f52 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22604 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-17mem-cache: Add more compression statsDaniel R. Carvalho
Add stats to calculate the total number of compressions, decompressions and the average compression size, in number of bits. Change-Id: I5eb563856c1ff54216e1edcd2886332b7481cbfe Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22609 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-17mem-cache: Factor out multiple block evictionDaniel R. Carvalho
Create a function to try to evict multiple blocks while checking for transient state. Change-Id: I6a879fa5e793cd92c4bdf4a258a133de4c865012 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22607 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-15arch-arm: ELIsInHost, check VHE and SecEL2Adrian Herrera
This patch modifies ELIsInHost to correctly check for VHE and Secure EL2 implementation. Change-Id: I947dddfc6761794493fef3d59b3b35754d07ed6b Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24046 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-15arch-arm: Virtualization Host Extensions checkingAdrian Herrera
This patch adds Armv8.1-VHE checking. This is based on the bit ID_AA64MMFR1_EL1.VH being 0b1. Change-Id: Ia3f278c63fe1b5448a686db87a46853fc8b6bea5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24045 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-14mem-garnet: Use smart pointers for CrossbarSwitch's membersDaniel R. Carvalho
Use smart pointers for the pointers managed by CrossbarSwitch. Change-Id: I71958c72cde5981d730aa3f68bba0ffbe4c2506f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24244 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-14x86: Stop clearing RAX for BIST in initCPU.Gabe Black
This doesn't actually change any behavior since RAX was being zeroed anyway, but since we don't and almost certainly never will have a BIST and the BIST is optional even in real hardware, we can drop it and simplify initCPU a little further. This reduces x86's initCPU function to just an invocation of InitInterrupt's invoke. Change-Id: I56b1aae2c1a738ef7ffabcf648dd7d0fb819d4e0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24187 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2020-01-14x86: Move local APIC initialization out of initCPU.Gabe Black
The APIC can (and probably should) set its version register on its own. Also it already configures its CPUID register when associated with a CPU and doesn't need initCPU to do that. Change-Id: I4611563668d197c48caf2f23fcde9ec2ec101fe7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24186 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2020-01-14x86: Move miscreg initialization to the ISA class.Gabe Black
The initCPU function was setting a lot of values to zero or other initial values, but that's something the ISA object can do as part of its clear() method. This gets rid of a lot of code that was individually zeroing registers, and also centralizes responsibility for those registers in the ISA. Change-Id: Iafcffd3f9329c39f77009b38b1696f91c36c117e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24185 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-13sim: Add a dumpSimcall mechanism to GuestABI.Gabe Black
This dumps a signature for a simcall as if it was going to be invoked, and can be used for debugging. Change-Id: I6262b94ad4186bac8dc5a1469e9bb3b8ae9d34e1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23460 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-13sim: Add a unit test for the GuestABI mechanism.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I76934d94b4c61570a4ca603388012c65280e2b7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23197 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-13sim: Implement a varargs like mechanism for GuestABI system.Gabe Black
This will let a function called with a GuestABI emulate the ... mechanism available in C. To make that possible without the functions knowing anything about the ABI and to follow C++'s (sensible) templating and virtual function rules, you have to tell VarArgs what types you might want to extract from it, unlike the pure ... varargs style mechanism. Also unlike ..., there is no mechanism in place to force the varargs to appear last in the argument list. It will pick up the progress through the arguments at the point it's reached, and will ignore any later arguments. It would be possible to be more rigorous about this by changing the callFrom templates, but the overhead in complexity is probably not worth it. Also, retrieving arguments through a VarArgs happens live, meaning at the point that the argument is asked for. If the ThreadContext or memory the argument lives in is modified before that point, the retrieved value will reflect that modification and not what the function was originally called with. Care should be taken so that this doesn't cause corrupted arguments. Finally, this mechansim (and the Guest ABI mechanism in general) is complex and should have tests written for it. That should be possible since ThreadContext is forward declared and so the test can say it works however it wants or even ignore it completely. If that changes in the future, we may need a mock ThreadContext implementation. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I37484b50a3e8c0d259d9590e32fecbb5f76670c1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23195 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-13systemc: keep SC_CONCAT* macroEarl Ou
Call of TLM_DECLARE_EXTENDED_PHASE requires SC_CONCAT* macros. This change keeps those macros to avoid compile errors. Change-Id: I573c4c126a350ef1a752d1c50658e7d9cedaaeae Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24123 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-11arch: Make the generic micropc enabled PCState set nupc to 1.Gabe Black
The default constructor of the micropc enabled generic PCState class set the next micropc to 0, when the non-default constructor and at least the x86 initCPU utility function set it to 1. This makes more sense since either the micropc doesn't matter as a concept if the instruction isn't microcoded, or, unless redirected by a micropc branch, you're going to want to execute the next microop and not just repeat the first one. Change-Id: I418ea986a071453563c4c8aad4fc4eb4f7beb641 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24184 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-10dev-arm: VExpress_GEM5_Base, fix daughterboard referenceAdrian Herrera
VExpress_GEM5_Base states that its memory map is based on CoreTile Express A15x2 A7x3, while the model used for the Daughterboard Configuration Controller (DCC) is based on Coretile Express A15x2. These two daughterboard specifications differ in both on-chip memory map and DCC clocks as of the TRMs. This patch makes the reference consistent to Coretile Express A15x2 and adds several non-confidential references to aid in understanding the platform and adding new peripherals. Change-Id: Ia55e7362bdc9ed6509f8eff4cbd7eb38e538d774 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24203 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-09tests,base: Added GTest for base/socket.ccBobby R. Bruce
It should be noted that some features of this class have not been fully tested due to interaction with system-calls. Change-Id: I8315188327e022ac4c98aa9ce4bd38243266ab17 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23984 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-09tests: Updated gtest/logging.cc to print log rather than fail.Bobby R. Bruce
Previously the `GTestExitLogger.log` function utilized GTest's `ADD_FAILURE_AT` macro. This meant, whenever `GTestExitLogger.log` were called, the calling test would be fail. This is problematic when trying to test code we expect to fail (i.e., when testing the error handling code is working correctly). Therefore, the `log` function now writes to stderr. The `GTestExitLogger` class is used by the `panic` and `fatal` loggers when running GTests. Instead of callnig `exit(1)` they throw a GTest exception, which can be captured in a test using `EXPECT_ANY_THROW(expection_thrower())`. Catching and verifying error logs can be done via: ``` testing::internal::CaptureStderr(); /* * "exception_thrower()" is a method we'd expect to call `fatal` or * `panic`, and therefore exit the simulation with a non-zero exit * code. When running via GTest, an exception is thrown instead. */ EXPECT_ANY_THROW(exception_thrower()); EXPECT_EQ("<error message>", testing::internal::GetCapturedStderr())); ``` Change-Id: I84a5f86bc573668d3dd5b40f626b43108dddb8e9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23983 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-09base: Include some required headers in amo.hh.Gabe Black
amo.hh was using several non-default definitions including std::function, uint8_t, and std::array without including any headers at all, and instead apparently relying on those having already been brought in by an earlier include. This change adds those includes explicitly. Change-Id: I92166ff581e74bd705e10fd4fa454df179ae1a97 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24183 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-09base, gpu-compute: Move gpu AMOs into the generic headerGiacomo Travaglini
Change-Id: I10d8aeaae83c232141ddd2fd21ee43bed8712539 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23565 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-08arch, base: Move arm AtomicOpFunctor into the generic headerGiacomo Travaglini
These AtomicGenericxOp functors are not arm specific: They just define a set of different functors depending on the number of operands they are using. Change-Id: Ida75066823c7718aee05717194cdb8225b700c5d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23564 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-08base: Move AtomicOpFunctors to a dedicated headerGiacomo Travaglini
src/base/types.hh file definition is: /** * @file * Defines global host-dependent types: * Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t. */ I feel AtomicOpFunctor doesn't fall in this cathegory so I am moving those into a dedicated header: base/amo.hh Change-Id: I8f05fb0944c03e4053cfaf2ffe65cac803df1d93 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23563 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
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