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2010-08-25ARM: Use fewer micro-ops for register update loads if possible.Gene WU
Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination regsiter. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict.
2010-08-25ARM: Set the high bits in the part number so it's considered new by some code.Ali Saidi
2010-08-25ARM: Fix VFP enabled checks for mem instructionsAli Saidi
2010-08-25ARM: Seperate out the renamable bits in the FPSCR.Gabe Black
2010-08-25ARM: Eliminate some unused enums.Gabe Black
2010-08-25ARM: Fix type comparison warnings in Neon.Gabe Black
2010-08-25ARM: Implement CPACR register and return Undefined Instruction when FP ↵Gabe Black
access is disabled.
2010-08-25ARM: Implement all ARM SIMD instructions.Gabe Black
2010-08-25ARM: Expand the mode checking utility functions.Gabe Black
inUserMode now can take either a threadcontext or a CPSR value directly. If given a thread context it just extracts the CPSR and calls the other version. An inPrivelegedMode function was also implemented which just returns the opposite of inUserMode.
2010-08-25Tracing: Fix trace so 'Predicated False' doesn't show upAli Saidi
2010-08-25mem: fix dumb typo in copyrightsSteve Reinhardt
2010-08-24testers: move testers to a new directoryBrad Beckmann
This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. --HG-- rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
2010-08-24MOESI_hammer: fixed bug for dma reads in single cpu systemsBrad Beckmann
2010-08-23Faults: Get rid of some commented out code in sim/faults.hh.Gabe Black
2010-08-23X86: Create a directory for files that define register indexes.Gabe Black
This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh
2010-08-23Power: Get rid of unused checkFpEnableFault.Gabe Black
This function was brought in from another ISA and doesn't actually do anything or get used.
2010-08-23ISA: Get rid of old, unused utility functions cluttering up the ISAs.Gabe Black
2010-08-23X86: Get rid of the flagless microop constructor.Gabe Black
This will reduce clutter in the source and hopefully speed up compilation.
2010-08-23X86: Make the TLB fault instead of panic when something is unmapped in SE mode.Gabe Black
The fault object, if invoked, would then panic. This is a bit less direct, but it means speculative execution won't panic the simulator.
2010-08-23X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR.Gabe Black
--HG-- rename : src/arch/x86/types.hh => src/arch/x86/types.cc
2010-08-23X86: Define a noop ExtMachInst.Gabe Black
2010-08-23X86: Mark serializing macroops and regular instructions as such.Gabe Black
2010-08-23X86: Add a .serializing directive that makes a macroop serializing.Gabe Black
This directive really just tells the macroop to set IsSerializing and IsSerializeAfter on its final microop.
2010-08-23X86: Consolidate extra microop flags into one parameter.Gabe Black
This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor.
2010-08-23CPU: Make the constants for StaticInst flags visible outside the class.Gabe Black
2010-08-23O3: Skipping mem-order violation check for uncachable loads.Min Kyu Jeong
Uncachable load is not executed until it reaches the head of the ROB, hence cannot cause one.
2010-08-23ARM: Improve printing of uop disassembly.Min Kyu Jeong
2010-08-23ARM: Clean up flattening for SPSR addingMin Kyu Jeong
2010-08-23ARM: Implement DBG instruction that doesn't do much for now.Gene Wu
2010-08-23MEM: Make CLREX a first class request operation and clear locks in caches ↵Gene Wu
when it in received
2010-08-23ARM: Make sure that software prefetch instructions can't change the state of ↵Gene Wu
the TLB
2010-08-23ARM: Don't write tracedata on writes, it might have been freed already.Gene Wu
2010-08-23ARM: Implement CLREX init/complete acc methodsGene Wu
2010-08-23ARM: Fix Uncachable TLB requests and decoding of xn bitGene Wu
2010-08-23Devices: Allow a device to specify that a request is uncachable.Gene Wu
2010-08-23ARM: For non-cachable accesses set the UNCACHABLE flagGene Wu
2010-08-23ARM: Implement DSB, DMB, ISBGene Wu
2010-08-23ARM: Get SCTLR TE bit from reset SCTLRGene Wu
2010-08-23ARM: Implement CLREXGene Wu
2010-08-23ARM: BX instruction can be contitional if last instruction in a IT blockGene Wu
Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond.
2010-08-23CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflagMin Kyu Jeong
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory ↵Min Kyu Jeong
instructions
2010-08-23ARM: mark msr/mrs instructions as SerializeBefore/AfterMin Kyu Jeong
Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR
2010-08-23O3: Handle loads when the destination is the PC.Min Kyu Jeong
For loads that PC is the destination, check if the load was mispredicted again when the value being loaded returns from memory
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false.
2010-08-23ARM: adding genMachineCheckFault() stub for ARM that doesn't panicMin Kyu Jeong
2010-08-23ARM: DFSR status value for sync external data abort is expected to be 0x8 in ↵Gene Wu
ARMv7
2010-08-23ARM: Temporary local variables can't conflict with isa parser operands.Gene Wu
PC is an operand, so we can't have a temp called PC
2010-08-23ARM: Exclusive accesses must be double word alignedAli Saidi
2010-08-23ARM: Add some registers for big loads/stores to support neon.Ali Saidi