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2019-02-22python: Fix param -> int conversion issuesAndreas Sandberg
Python 3 doesn't convert params to integers automatically in range(). Add __index__ to CheckedInt to enable implicit conversions again. Add explicit conversions where necessary. Change-Id: I2de6c9906d3bb7616f12ada6728b9e4b1928511c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16000 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-22cpu-o3: Add cache read ports limit to LSQGabor Dozsa
This change introduces cache read ports to limit the number of per-cycle loads. Previously only the number of per-cycle stores could be limited. Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13517 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-22python: Make iterator handling Python 3 compatibleAndreas Sandberg
Many functions that used to return lists (e.g., dict.items()) now return iterators and their iterator counterparts (e.g., dict.iteritems()) have been removed. Switch calls to the Python 2.7 iterator methods to use the Python 3 equivalent and add explicit list conversions where necessary. Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15992 Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-22python: Add missing operators to NumericParamValueAndreas Sandberg
Add missing operators to NumericParamValue and ensure that they are able to work on the underlying value if the right hand side is a param. Change-Id: I2bd86662aee9891bbd89aed7ebe20b827b5528bd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16001 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-22mem-cache: Add a mechanism to iterate all entries of an AssociativeSetJavier Bueno
Added functions to obtain an iterator to access all entries of an AssociativeSet container. Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26 Reviewed-on: https://gem5-review.googlesource.com/c/16582 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-21scons: Add a convenience method to set RPATH for local libraries.Gabe Black
When linking in a dynamic library which is in the gem5 build directory, it's useful to set RPATH so that you don't have to set LD_LIBRARY_PATH when you run gem5 so that the dynamic linker can find it. Since it's tricky and not entirely obvious how to set up those paths correctly, this change adds a small convenience function which does that for you. It also handles situations where the same dynamic library may be linked into different binaries in different directories which each need a different relative RPATH. It does that by letting the environment for each binary set a construction variable which says how to get from that particular binary back to the build directory. This helper method then sets RPATH to start at $ORIGIN (the binary), to follow that relative path to the variant build directory, and then the per-library but not per-binary path to the library's directory. This change also adds the -z origin linker flag which makes the linker handle $ORIGIN properly. Change-Id: I45f4d72cd14396a73e0b963cea6a39d9bfb7f984 Reviewed-on: https://gem5-review.googlesource.com/c/16566 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-21systemc: Make the verify.py script work when run from different dirs.Gabe Black
The verify.py script ran scons from the CWD, and that would fail if there wasn't a SConstruct in that directory, ie if it wasn't from the source of the checkout. This change makes verify.py use scons' --directory option to run from where the SConstruct is, or at least the SConstruct which was checked out alongside that copy of verify.py. That location can be overridden using the new -C or --scons-dir options. Change-Id: I9f033d6dd30e0c2992b7f3102c573b34ea9c49e0 Reviewed-on: https://gem5-review.googlesource.com/c/16562 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-21systemc: Make sc_(pause|stop) exit to python when not using sc_main.Gabe Black
In those cases, there's no sc_main to return control to. The python config script is serving more or less the same purpose, so we can return control to there instead. Change-Id: I3cf0623ae51d989b883fb8556ebbf44651bbec99 Reviewed-on: https://gem5-review.googlesource.com/c/16445 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-21systemc: Init some values in the scheduler for running without sc_main.Gabe Black
When running without sc_main, sc_start won't be called, and therefore runToTime and maxTick won't be initialized. To avoid the scheduler getting confused and behaving erratically, those values should be initialized to something that makes sense in situations where there's no sc_main. Change-Id: I6ddd7db9ecb36d716eb5ef75e1c38bb99a386092 Reviewed-on: https://gem5-review.googlesource.com/c/16443 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-21systemc: Handle exceptions "correctly" even if sc_main hasn't been run.Gabe Black
If sc_main hasn't run, for instance if there isn't an sc_main and gem5 is orchestrating the simulation directly, then exceptions shouldn't be thrown to the sc_main fiber since it isn't running and may not be able to run since sc_main may not even exist. Instead, we need to check whether it makes sense to throw to sc_main, and if not pass the exception directly to the report handler since there likely won't be anyone to catch it if we just throw it from the scheduler or into general purpose gem5. Since the name throwToScMain is no longer a complete description for what that function does, this change renames it to throwUp, since it will now throw exceptions up the stack, either to sc_main or to the conceptual top level by going directly to the report handler. Change-Id: Ibdc92c9cf213ec6aa15ad654862057b7bf2e1c8e Reviewed-on: https://gem5-review.googlesource.com/c/16442 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-21mem-cache: Added the Slim AMPM PrefetcherJavier Bueno
Reference: Towards Bandwidth-Efficient Prefetching with Slim AMPM. Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship. Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already in gem5). Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a Reviewed-on: https://gem5-review.googlesource.com/c/16383 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-20python: Fix Param initialization issue in Python 3Andreas Sandberg
When initializing a param with a SimObject NULL pointer, convert() checks if the 'ptype' attribute has been created and whether the value is NULL. In that case, it assumes that the object is being initizalized as a part of SimObject initialization and defers the conversion. This check is implemented using hasattr() which in turn is implemented using the __getattr__ implementation that asserts because all SimObjects haven't been initialized yet. Implement the check using a lookup in the object's dictionary instead to prevent the SimObject lookup. Change-Id: I7367563c4fb71f6d2be541ebdc0be418e9f73d48 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15990 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-20python: Use __name__ instead of func_name for Py3 compatAndreas Sandberg
Change-Id: I62a9685b4bce7e9012bc65309fcafe26135fde6d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15997 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-20python: Add __bool__ helpers in addition to __nonzero__Andreas Sandberg
Python 3 uses __bool__ instead of __nonzero__ when performing a Boolean comparison. Change-Id: I85185bbe136ecae67346fa23569e24edd7329222 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-20config: Make parameter conversion handle integers in other bases.Gabe Black
Python's float() function/type can't handle hexadecimal notation, but int() can. Since there are also cases where converting to a float and then back to an int (or long) can cause rounding error, this change splits toFloat and toInteger apart and makes them call a worker function which accepts a conversion function which does the work of converting a numeric string into an actual number. in the case of toFloat, it still uses the standard float(), and in the case of toInteger it uses a lambda which wraps int(x, 0). Change-Id: Ic46cf4ae86b7eba6f55d731d1b25e3f84b8bb64c Reviewed-on: https://gem5-review.googlesource.com/c/16504 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-20x86: Call the base class's regStats in X86ISA::TLBBagus Hanindhito
When I try to build x86 architecture and run the se.py sample script with helloworld example, there is a panic warning stated "Not all stats have been initialized. You may need to add <ParentClass>::regStats() to a new SimObject's regStats() function." I see that in x86 tlb.cc, there is no initialization in regStats() function that causes memory allocation error in some machine which make gem5 exit abnormally. I add the BaseTLB::regStats(); on TLB::regStats() method and can solve the problem Change-Id: I8b62bebc15f896c3136ff4f8253dabbf998f618f Reviewed-on: https://gem5-review.googlesource.com/c/16522 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-19sim: Add a mechanism to exit the simulation loop immediately.Gabe Black
There are some cases, specifically when running systemc, that it's necessary to exit the simulation loop immediately rather than finishing running events scheduled for the current Tick. When running under sc_main, sc_stop and sc_pause return control to sc_main which can happen immediately. When running without sc_main, control needs to return to the python config script which needs to happen through a global exit event. Since sc_pause and sc_stop are supposed to stop simulation without necessarily letting all the events at the current time run, we need a way to schedule an exit event with a very high priority (rather than a very low priority). This change adds a new exitSimLoopNow function which does that, and adds a new constructor to the GlobalSimLoopExitEvent which uses that priority. Also, a couple of cruft functions from the sim events are removed. Change-Id: Icfbec17fb10f98084a75740acd839dbf4096fbb3 Reviewed-on: https://gem5-review.googlesource.com/c/16444 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-19cpu: Add ISA* getter in Thread interfaceGiacomo Gabrielli
This patch is adding a ISA* getter to the TC interface Change-Id: Ib8ddc5d8fdd44e782f50a2ad15878a6bcf931e58 Reviewed-on: https://gem5-review.googlesource.com/c/16462 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-02-18arch-generic: Making base TLB class a MemObjectIvan Pizarro
Allow configuring a TLB hierarchy using ports Change-Id: I1f791829d4e072a9104e67eacf69a69de9543634 Reviewed-on: https://gem5-review.googlesource.com/c/14117 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-18arch-arm: Move GICv3 detection at startup timeGiacomo Travaglini
At the moment the haveGicV3 parameter is used only to signal its presence when reading the MISCREG_ID_AA64PFR0_EL1 register. It depends on the system->getGIC pointing to a GICv3 model. However this pointer is set in the System only at init time (after construction), which means that the haveGICv3CPUInterface will always be false. This patch is fixing this by moving the parameter initialization at startup time, together with the cpu interface registration. Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16483 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-18dev-arm: LPI support for GICv3. This doesn't include an ITS model.Jairo Balart
Change-Id: Ia2c02cca4f95672d6361fba16201a56e2047ddb7 Reviewed-on: https://gem5-review.googlesource.com/c/16142 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-18base: Fix enums checkpointingGiacomo Travaglini
Creating an extra version of string to number converters (__to_number) in base/str.hh; it will be used by enums only when unserializing them. The reason not to have a single helper for both enums and integers is that std::numeric_limits trait is not specialized for enums. We fix this by using the std::underlying_type trait. Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16382 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-15cpu: Fix fast build broken due to unused variableGiacomo Travaglini
This fixes fast build for commit 25dc765889d948693995cfa622f001aa94b5364b (fast build is striping out assertions) Change-Id: I9536ad58a3d85990b16a1f8c2515f6bf5d3acf71 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16463 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-14systemc: Add a systemc_home directory which maps to the ext headers.Gabe Black
Some systemc code bases expect to find a SYSTEMC_HOME environment variable which points to the installed header files provided by systemc, all under ${SYSTEMC_HOME}/include. The systemc headers in gem5 are not supposed to be installed anywhere, but to satisfy those expectations this change creates a dummy systemc_home directory with an include/ in it which has headers which just include the actual headers in src/systemc/ext. More gem5 aware code bases can still access the headers either by letting gem5's scons environment -I the ext directory, or can do so themselves if they're not being built by gem5's scons. Change-Id: I5f2e6bfcf20dd314d525207c2e13ca53474a33f3 Reviewed-on: https://gem5-review.googlesource.com/c/16263 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-14systemc: Make an include in src/systemc/ext use a relative path.Gabe Black
The includes in src/systemc/ext are supposed to use relative paths so that they can be included in other bodies of code which aren't based in gem5 and don't share it's -I-s, or potentially even have access to anything outside of src/systemc/ext. Change-Id: Icde457329c2c4ab4689221015bfcfe2ff8b051f0 Reviewed-on: https://gem5-review.googlesource.com/c/16262 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-13cpu: Added 8KB and 64KB TAGE-SC-L branch predictorJavier Bueno
The original paper of the branch predictor can be found here: http://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf Change-Id: I684863752407685adaacedebb699205c3559c528 Reviewed-on: https://gem5-review.googlesource.com/c/14855 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-13python: Remove uses of tuple unpacking in function paramsAndreas Sandberg
Python 3 doesn't support tuple unpacking in function parameters and lambdas. Change-Id: I36c72962e33a9ad37145089687834becccc76adb Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15991 Reviewed-by: Gabe Black <gabeblack@google.com>
2019-02-13python: Replace deprecated repr syntaxAndreas Sandberg
Change-Id: I5f9538cf2ca5ee17c51e7c5388d3aef363fcfa54 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15989 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-13python: Switch from using compare to key in list sortAndreas Sandberg
Python 3 has deprecated the use of a comparison function in favour of a key extraction function. Change-Id: I4b7eab791ecbdfbf7147f57fdbc7cbe8f1de20dd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15995 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-13sim-se: update the arm kernel versionAyaz Akram
This change is needed to run cpu tests with ARM binaries compiled with newer linux kernel headers Change-Id: I6cbf132c38d4b18f971ee32272ddb6a5a791a625 Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15855 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12python: Replace dict.has_key with 'key in dict'Andreas Sandberg
Python 3 has removed dict.has_key in favour of 'key in dict'. Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15987 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12python: Add missing defines importAndreas Sandberg
The _check_tracing helper function in main.py depends on defines to check if tracing has been enabled at compile time. This module is imported in main() but not at the module level, which breaks this function. Change-Id: I26d65a4320da8618e0e552553695884fd2c880e0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16402 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12python: Replace DictMixin with Mapping / MutableMappingAndreas Sandberg
Python 3 has removed support for DictMixin, so switch to Mapping / MutableMapping in collections which provides the same functionality. Change-Id: I61fbe366d2c9fc6e01b470f82f49cc02b99dec32 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15984 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-12python: Replace orderdict with collections.OrderedDictAndreas Sandberg
Python 2.7 and newer has support for ordered dictionaries in the standard library. Remove this custom class. Change-Id: I4b720405aa3c4ce8d5c0b401eefe744a85ac3a3e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16362 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-12python: Update use of exec to work with Python 3Andreas Sandberg
Python 3 uses 'exec(code, globals)' instead of 'exec code in globals'. Switch to the newer syntax since it is supported by Python 2.7. Also, move check_tracing out of main to work around a bug in Python 2.7. Change-Id: I6d390160f58783e1b038a572b64cdf3ff09535fa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15986 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-12python: Switch to using open instead of fileAndreas Sandberg
Python 3 doesn't support the file(name, mode) syntax which has been deprecated in favour of open. Change-Id: I35ef8690d97a5243860a64ff985fd22fa86253f1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15985 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12mem-cache: Irregular Stream Buffer PrefetcherJavier Bueno
Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Reviewed-on: https://gem5-review.googlesource.com/c/15215 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-02-12mem-cache: Added the Delta Correlating Prediction Tables PrefetcherJavier Bueno
Reference: Multi-level hardware prefetching using low complexity delta correlating prediction tables with partial matching. Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010. In Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers (HiPEAC'10) Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d Reviewed-on: https://gem5-review.googlesource.com/c/16062 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12arch-mips: Remove unused Python fileAndreas Sandberg
Change-Id: I7155915fccdec1d9f116f2a8617474188a91165b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16302 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-12python: Make exception handling Python 3 safeAndreas Sandberg
Change-Id: I9c2cdfad20deb1ddfa224320cf93f2105d126652 Reviewed-on: https://gem5-review.googlesource.com/c/15980 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12python: Fix native module initialisation on Python 3Andreas Sandberg
The approach we currently use to register our native modules doesn't work on Python 3. Convert the code to use the Python inittab instead of the old ad-hoc method. Change-Id: I961f8a33993c621473732faeaab955a882769a4b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15979 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2019-02-12mem-ruby: Fixing TopologyPouya Fotouhi
The constructor assumes the number of nodes (i.e. controllers) equal to the number of external nodes. This is a not necessarily valid for all cases (e.g MESI_Three_Level - where L0s are directly connected to L1s). MachineType_base_number(MachineType_NUM) provides the total number of controllers. Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: Id906099dc967ec70aa34dedb0b55351031ff242c Reviewed-on: https://gem5-review.googlesource.com/c/15716 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-12mem-ruby: Fixing MESI Three LevelPouya Fotouhi
Adding back some changes done in patch 676ae57827. Transient state IS_I, STALE_DATA, Data_Stale event are necessary. Issue: (cacheline A, initial state for P0 and P1 is I) | P0 | P1 | |GETX (A)| | | |GETS (A)| |Inv_All | | P1 never sends the ACK - deadlock It should ACK, later upon data use it as stale data, and got to I. Solution: P1(A): GETS: I->IS Inv_All: IS->IS_I, Send ACK Data: IS_I->I, STALE_DATA to L0 Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: I1e7b2c05439d08579c68d8eb444e0f332e75e07f Reviewed-on: https://gem5-review.googlesource.com/c/15715 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-11systemc: Change the type of a loop counter to avoid a warning.Gabe Black
g++ complained about comparing an signed int loop counter with the return value of a size() function. This change changes it to an unsigned to make g++ happy/quiet. Change-Id: I28fa79c448465b24d77b5623860f9b991f313561 Reviewed-on: https://gem5-review.googlesource.com/c/16286 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-11scons: Change an = to a += when accumulating sources from filters.Gabe Black
The loop accidentally used a = when it should have used a +=, meaning only the sources from the final filter would be used. Change-Id: Ie066a5f85696f05d9ad3cf61f928b12deb39475b Reviewed-on: https://gem5-review.googlesource.com/c/16285 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-11systemc: scons: Specify RPATH as a list.Gabe Black
scons will attempt to use insert() on the value of RPATH when adding in additional values. That will fail if RPATH is a Literal. Change-Id: I9da75c6b189f12843a3452cdf92f7b56c0ec340b Reviewed-on: https://gem5-review.googlesource.com/c/16284 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-08cpu: Proposal for changing the indirect branch predictor interfaceJairo Balart
Now the indirect branch predictor handles its own GHR instead of getting the one from the direction predictor. Also, now the commit method of the indirect predictor is called for every pending branch on an update, as the indirect predictors may want to update their interal structures/histories with the information of each branch. Change-Id: I7053fbea42a53960a3bc1ba32912cc99c160511e Reviewed-on: https://gem5-review.googlesource.com/c/15318 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-08riscv: fix AMO, LR and SC instructionsTuan Ta
(1) Atomic Memory Operation (AMO) This patch changes how RISC-V AMO instructions are implemented. For each AMO, instead of issuing a locking load and an unlocking store request to downstream memory system, this patch issues a single memory request that contains a corresponding AtomicOpFunctor to the memory system. Once the memory system receives the request, the atomic operation is executed in one single step. This patch also changes how AMO instructions handle acquire and release flags in AMOs (e.g., amoadd.aq and amoadd.rl). If an AMO is associated with an acquire flag, a memory fence is inserted after the AMO completes as a micro-op. If an AMO is associated with a release flag, another memory fence is inserted before the AMO executes. If both flags are specified, the AMO is broken down into a sequence of 3 micro-ops: mem fence -> atomic RMW -> mem fence. This change makes this AMO implementation comply to the release consistency model. (2) Load-Reserved (LR) and Store-Conditional (SC) Addresses locked by LR instructions are tracked in a stack data structure. LR instruction pushes its target address to the stack, and SC instruction pops the top address from the stack. As specified by RISC-V ISA, a SC fails if its target address does not match with the most recent LR. Previously, there was a single stack for all hardware thread contexts. A shared stack between thread contexts can lead to a infinite sequence of failed SCs if LRs from other threads keep pushing new addresses to this stack. This patch gives each context its private stack to address the problem. This patch also adds extra memory fence micro-ops to lr/sc to guarantee a correct execution order of memory instructions with respect to release consistency model. Change-Id: I1e95900367c89dd866ba872a5203f63359ac51ae Reviewed-on: https://gem5-review.googlesource.com/c/8189 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2019-02-08cpu: support atomic memory request type with AtomicOpFunctorTuan Ta
This patch enables all 4 CPU models (AtomicSimpleCPU, TimingSimpleCPU, MinorCPU and DerivO3CPU) to issue atomic memory (AMO) requests to memory system. Atomic memory instruction is treated as a special store instruction in all CPU models. In simple CPUs, an AMO request with an associated AtomicOpFunctor is simply sent to L1 dcache. In MinorCPU, an AMO request bypasses store buffer and waits for any conflicting store request(s) currently in the store buffer to retire before the AMO request is sent to the cache. AMO requests are not buffered in the store buffer, so their effects appear immediately in the cache. In DerivO3CPU, an AMO request is inserted in the store buffer so that it is delivered to the cache only after all previous stores are issued to the cache. Data forwarding between between an outstanding AMO in the store buffer and a subsequent load is not allowed since the AMO request does not hold valid data until it's executed in the cache. This implementation assumes that a target ISA implementation must insert enough memory fences as micro-ops around an atomic instruction to enforce a correct order of memory instructions with respect to its memory consistency model. Without extra memory fences, this implementation can allow AMOs and other memory instructions that do not conflict (i.e., not target the same address) to reorder. This implementation also assumes that atomic instructions execute within a cache line boundary since the cache for now is not able to execute an operation on two different cache lines in one single step. Therefore, ISAs like x86 that require multi-cache-line atomic instructions need to either use a pair of locking load and unlocking store or change the cache implementation to guarantee the atomicity of an atomic instruction. Change-Id: Ib8a7c81868ac05b98d73afc7d16eb88486f8cf9a Reviewed-on: https://gem5-review.googlesource.com/c/8188 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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