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2019-02-01dev, arm: Removed contextId variableAnouk Van Laer
The contextId variable is only used by the debug flag and will prevent a more optimised binary (i.e. fast) from compiling. Change-Id: I6cefb5bc06d0d4b415df62f1278db53ba309fb87 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16042 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
Most architectures weren't using the CCReg type, and in x86 and arm it was already a uint64_t. Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6 Reviewed-on: https://gem5-review.googlesource.com/c/14515 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31python: Remove getCode() type workaroundAndreas Sandberg
Python 2.7 requires a workaround when wrapping exit objects to explicitly convert the return of getCode() to int to not confuse sys.exit. This workaround isn't needed and doesn't work on Python 3 since it doesn't have a separate long integer type. Change-Id: I57bc3fd8f4699676c046ece8a52baa2796959ffd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15978 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-31sim: Prepare C++ side for Python 3Andreas Sandberg
Python 3 uses wide strings instead of ordinary strings for many APIs. Add the necessary conversions to comply with the new API. Change-Id: I6f45c9c532537d50d54b542f34eb8fd8cb375874 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15977 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-31power: Get rid of some ISA specific register types.Gabe Black
Change-Id: If63acb10705a9f442255680917d16630748ca8e1 Reviewed-on: https://gem5-review.googlesource.com/c/14465 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31null: Get rid of some register type definitions.Gabe Black
These are no longer used. Change-Id: Ic6a35e8a7e25eab9d21a3eef683914e01508c6d7 Reviewed-on: https://gem5-review.googlesource.com/c/14463 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31mips: Stop using architecture specific register types.Gabe Black
Change-Id: I764f6eea214ba4e03cc0fe19a21abcb0ebd04408 Reviewed-on: https://gem5-review.googlesource.com/c/14462 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31alpha: Stop using architecture specific register types.Gabe Black
Change-Id: I4052000014c9f6f9ecefd3f37e58595c61599484 Reviewed-on: https://gem5-review.googlesource.com/c/14461 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31x86: Stop using/defining some ISA specific register types.Gabe Black
These have been replaced with the generic RegVal type. Change-Id: I75c1134212067dea43aa0903d813633e06f3d6c6 Reviewed-on: https://gem5-review.googlesource.com/c/14476 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31riscv: Get rid of some ISA specific register types.Gabe Black
Change-Id: Ie812cf1d42536094273ba2ec731c16cca38db100 Reviewed-on: https://gem5-review.googlesource.com/c/14466 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
Now that there's no plain FloatReg, there's no reason to distinguish FloatRegBits with a special suffix since it's the only way to read or write FP registers. Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded Reviewed-on: https://gem5-review.googlesource.com/c/14460 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector Extension (SVE), introduce the notion of a predicate register file. This changeset adds this feature across architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13715 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-30arch-arm, configs: Create single instance of DTB autogenerationGiacomo Travaglini
This patch is rewriting the DTB autogeneration functions available in fs_bigLITTLE.py and fs.py as a single method in the GenericArmSystem so that other configuration scripts can make use of it. Change-Id: I492bbf77e6b0ac5c5fbdbc75c0eecba29bd63bda Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15958 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Remove floatReg operand typeGiacomo Travaglini
Change-Id: I87553257ce9c42d0e2514d5a1f010bc6e2e7f21e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15604 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Use VecElem instead of FloatReg for FP instructionGiacomo Travaglini
SIMD & FP Operations use FloatRegs in AArch32 mode and VecRegs in AArch64 mode. The usage of two different register pools breaks interprocessing between A32 and A64. This patch is changing definition of arm operands so that they are backed by VecElems in A32, which are mapped to the same storage as A64 VecRegs. Change-Id: I54e2ea0ef1ae61d29aca57ab09acb589d82c1217 Reviewed-on: https://gem5-review.googlesource.com/c/15603 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch: Fix VecElem Operand generation in ISA parserGiacomo Travaglini
Fixes include: * Change of reg_class: VecElemClass in lieau of non-existing VectorElemClass. * Removal of unused regId in operand constructor * makeRead and makeWrite are using VecElem (which is a typedef of uint32_t) as a source/destination type, regardless of the real operand type (which is specified by ctype) Change-Id: I4588e1120e1fc8fdb68b2b2f05d5e3692c55b2e8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15602 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601
2019-01-25cpu: O3 rename using the flatIndex instead of indexGiacomo Travaglini
This patch is replacing the RegId::index with RegId::flatIndex so that it provides a valid register number when used by a VecElem register. Change-Id: I5b000abb9457cd325c2a3021e772a75ea33d8a4c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15600 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Inital vector rename mode depending on A32/A64Giacomo Travaglini
Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481 Reviewed-on: https://gem5-review.googlesource.com/c/15599 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25cpu: Fix VecElemClass bugs in cpu modelsGiacomo Travaglini
This patch is: * Adding a missing VecElemClass entry * Fixing assertion in rename map which was checking the number of free vector registers rather than free vector element registers * Fixing assertion in read/setVecElemOperand APIs. * Using the right register index in SimpleThread * Using VecElem instead of VecReg on O3 readArchVecElem Change-Id: I265320dcbe35eb47075991301dfc99333c5190c4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15598 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25cpu: Add VecElem entries in MinorCPU ScoreboardGiacomo Travaglini
This patch is: * Increasing the number of bits in the Scoreboard so that it is keeping track of VecElemClass dependencies. * Fixing VecElemClass entry in the scoreboard table so that it correctly uses flatIndex rather than index. Change-Id: Ie4877e5fe410b1437447adebbe289602a443f7c0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15597 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Remove unused float operandsGiacomo Travaglini
Removing FaP1 and FDest2 since they are not currently used by any ARM instruction. Change-Id: I4251dfcdd3f4434caaf0bdab507c1c3bd53fb5d2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15596 Reviewed-by: Ciro Santilli <ciro.santilli@gmail.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch: Provide traceback when parsing ISA codeGiacomo Travaglini
There is no line information When the ISA code is executed inside the isa_parser environment and an error is encountered. The build stops and reports the line of the let block containing the error. This patch is enhacing the error reporting by printing the traceback of the faulting ISA code. Change-Id: I3acd17f0d78b2feb8fe6e48808a094c5b81624e6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15595 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-25python: Always throw TypeError on slave-slave connectionsNicholas Lindsay
params.py checks the validity of memory port-port connections before they are instantiated in C++. This commit ensures that attempting to connect two slave ports together will cause a TypeError. Change-Id: Ia7d0a15df28b96c7bf5e568c4f4917d21a19b824 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15896 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-24hsail: Remove the MiscReg type.Gabe Black
It has been replaced by the ISA agnostic RegVal. Change-Id: I563ea3852e37b5c1cf51eb0ac9a6f2a827ba89cf Reviewed-on: https://gem5-review.googlesource.com/c/14464 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-24base: arch: Get rid of the now unused FloatRegVal type.Gabe Black
This type is no longer used since FP registers are accessed as integer bit patterns. Change-Id: I1070f9443d6247165fd64c6bc041811c28287e9f Reviewed-on: https://gem5-review.googlesource.com/c/14459 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-24dev-arm: fix --generate-dtb for ARMCiro Santilli
Was failing with: NameError: global name 'FdtNode' is not defined The problem was introduced at: 75831ce5b7880b67c1aa2e0871ce16d5c01cadc7 Change-Id: I7e2ce0e5311e7814229945b9f4e7318a8652dc1f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15875 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-24cpu-o3: O3 LSQ GeneralisationRekai Gonzalez-Alberquilla
This patch does a large modification of the LSQ in the O3 model. The main goal of the patch is to remove the 'an operation can be served with one or two memory requests' assumption that is present in the LSQ and the instruction with the req, reqLow, reqHigh triplet, and generalising it to operations that can be addressed with one request, and operations that require many requests, embodied in the SingleDataRequest and the SplitDataRequest. This modification has been done mimicking the minor model to an extent, shifting the responsibilities of dealing with VtoP translation and tracking the status and resources from the DynInst to the LSQ via the LSQRequest. The LSQRequest models the information concerning the operation, handles the creation of fragments for translation and request as well as assembling/splitting the data accordingly. With this modifications, the implementation of vector ISAs, particularly on the memory side, become more rich, as the new model permits a dissociation of the ISA characteristics as vector length, from the microarchitectural characteristics that govern how contiguous loads are executing, allowing exploration of different LSQ to DL1 bus widths to understand the tradeoffs in complexity and performance. Part of the complexities introduced stem from the fact that gem5 keeps a large amount of metadata regarding, in particular, memory operations, thus, when an instruction is squashed while some operation as TLB lookup or cache access is ongoing, when the relevant structure communicates to the LSQ that the operation is over, it tries to access some pieces of data that should have died when the instruction is squashed, leading to asserts, panics, or memory corruption. To ensure the correct behaviour, the LSQRequest rely on assesing who is their owner, and self-destroying if they detect their owner is done with the request, and there will be no subsequent action. For example, in the case of an instruction squashed whal the TLB is doing a walk to serve the translation, when the translation is served by the TLB, the LSQRequest detects that the instruction was squashed, and as the translation is done, no one else expect to access its information, and therefore, it self-destructs. Having destroyed the LSQRequest earlier, would lead to wrong behaviour as the TLB walk may access some fields of it. Additional authors: - Gabor Dozsa <gabor.dozsa@arm.com> Change-Id: I9578a1a3f6b899c390cdd886856a24db68ff7d0c Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13516 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-23arch-arm: Implement LoadAcquire/StoreRelease in AArch32Giacomo Travaglini
This patch is implementing LoadAcquire/StoreRelease instructions in AArch32, which were added in ARMv8-A only and where not present in ARMv7. Change-Id: I5e26459971d0b183a955cd7b0c9c7eaffef453be Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15817 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23arch-arm: IsStoreConditional flag set depending on flavorGiacomo Travaglini
This patch is aligning A32 with A64 where the IsStoreConditional flag doesn't have to be specified manually in the instruction implementation, but will be automatically added to any exclusive store. Change-Id: Id02ed6fc2beeca6d125017393714a7c6eb3d8a33 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15816 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23arch-arm: Remove SWP and SWPB instructionsGiacomo Travaglini
The SWP and SWPB instructions have been removed from AArch32. It was previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits, which are now hardcoded to 0b0000 (SWP and SWPB not implemented) Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15815 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23systemc: Fix TLM related includes.Gabe Black
There are a couple things this CL fixes related to the TLM #includes. 1. Removes #includes of <systemc> and <tlm>. These bring in a header file from boost which shouldn't be necessary but which some of the tests (and likely some external code) depends on. We avoid including those in files built into gem5 itself so that gem5 isn't dependent on boost. 2. All includes in ext should be relative. That way those headers can be removed from gem5 and still build, allowing them to be moved over to or referenced from a foreign codebase which isn't part of gem5. Change-Id: I76e267385b48cb4fe93aea89ec8319c76465a0a4 Reviewed-on: https://gem5-review.googlesource.com/c/15796 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-23arm: Replace MiscReg with RegVal in utility.(hh|cc).Gabe Black
These uses snuck in after the previous pass which made this switch in the rest of these files. Change-Id: Ie891c6ec393a65f1c57c54301f0a2bb920d38bb0 Reviewed-on: https://gem5-review.googlesource.com/c/15795 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-23mem-ruby: Fix missing TBE allocation and deallocationZicong Wang
The TBE allocation and deallcation are currently missing during the directory state transition from I to M in protocol MI_example. Change-Id: If7569c02faf56ea84c34ee1345f1a33d318cdfff Signed-off-by: Zicong Wang <wangzicong@nudt.edu.cn> Reviewed-on: https://gem5-review.googlesource.com/c/15535 Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-22sparc: Get rid of some register type definitions.Gabe Black
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
These values are all basic integers (specifically uint64_t now), and so passing them by const & is actually less efficient since there's a extra level of indirection and an extra value, and the same sized value (a 64 bit pointer vs. a 64 bit int) is being passed around. Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3 Reviewed-on: https://gem5-review.googlesource.com/c/13626 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-22arm: Get rid of some register type definitions.Gabe Black
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435 Reviewed-on: https://gem5-review.googlesource.com/c/13625 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
Other dev code was already switched over. This code was written before the switch over (or unaware of it), and checked in after. Change-Id: Ibb9e9e4300d01cc46e4dae668274debc2a4989ba Reviewed-on: https://gem5-review.googlesource.com/c/15755 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22arch-arm: implement the GDB XML target description for ARMCiro Santilli
The supported registers are essentially the same as before this patch, but it is now trivial to make new registers visible in future commits. Change-Id: Id15b7aeccca824c342e49a626d2877179474f3d4 Reviewed-on: https://gem5-review.googlesource.com/c/15138 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22scons: add helpers to access GDB XML description filesCiro Santilli
Change-Id: Ic3b18887544b7710ed07a86d28dc62d8441b3476 Reviewed-on: https://gem5-review.googlesource.com/c/15255 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-22scons: allow embedding arbitrary blobs into the gem5 executableCiro Santilli
The initial motivation for this is to embed the GDB XML target description files into the executable. Change-Id: I721e8dd37119d8e6eb376d7e9050b1094282bacc Reviewed-on: https://gem5-review.googlesource.com/c/15136 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-22base: add support for GDB's XML architecture definitionCiro Santilli
This is done by implementing the Xfer:features:read packet of the GDB remote protocol. Before this commit, gem5 used the defaults of the GDB client. With this commit, gem5 can inform the client which registers it knows about. This allows in particular to support new registers which an older GDB client does not yet know about. The XML is not implemented in this commit for any arch, and falls back almost exactly to previous behaviour. The only change is that now gem5 replies to the Supported: request which the GDB clients sends at the beginning of the transaction with an empty feature list containing only the mandatory PacketSize= argument. Since the feature list does not contain qXfer:features:read, the GDB client knows that the gem5 server does support the XML format and uses its default registers as before. Change-Id: I5185f28b00e9b9cc8245f4b4262cc324c3d298c1 Reviewed-on: https://gem5-review.googlesource.com/c/15137 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22arch-arm: Move AArch32 IMPLEMENTATION DEFINED registersGiacomo Travaglini
Moving AArch32 instruction accessing IMPLEMENTATION DEFINED registers from pseudo.[cc/hh] to misc.[cc/hh] in order to symmetrically match with AArch64 implementation. Change-Id: I27b0d65925d7965589b765269ae54129426e4c88 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15735 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22mem: Add tryTiming suppport to CommMonitorSascha Bischoff
The CommMonitor did not support tryTiming, which resulted in gem5 panicing if the CommMonitor was used. With this change, we update the CommMonitor pass through the tryTiming() calls. Change-Id: I86810170e5e10a0c5d63af76fc4a6ab70710d2fb Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15736 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-22sim-se add readv and modifies writevBrandon Potter
Change-Id: I6cbce4389d5697da34058dc910306394e48c6582 Reviewed-on: https://gem5-review.googlesource.com/c/12117 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
Add getsockopt, getsockname, setsockname, and getpeername system calls. Change-Id: Ifa1d9a95f15b4fb12859dbfd3c4bd248de2e3d32 Reviewed-on: https://gem5-review.googlesource.com/c/12116 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
Fix poll so that it will use the syscall retry capability instead of causing a blocking call. Add the accept and wait4 system calls. Add polling to read to remove deadlocks that occur in the event queue that are caused by blocking system calls. Modify the write system call to return an error number in case of error. Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da Reviewed-on: https://gem5-review.googlesource.com/c/12115 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add calls for network transmissionsBrandon Potter
Add recvfrom, sendto, recvmsg, and sendmsg system calls. Change-Id: I2eb50ea7823c8af57d99b3b8d443d2099418c06c Reviewed-on: https://gem5-review.googlesource.com/c/12114 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add socket-based functionalityBrandon Potter
Add socket, socketpair, bind, list, connect and shutdown system calls. Change-Id: I635af3fca410f96fe28f8fe497e3d457a9dbc470 Reviewed-on: https://gem5-review.googlesource.com/c/12113 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-18base: Fix unitialized storageDaniel R. Carvalho
The bitunion is not being initialized on constructor to avoid performance overhead, and that generated a maybe-unitialized error when a sub-class was being copied before assigned in serialize's parseParam() in some compilers. This patch adds zero-initialization to the problematic variable to appease the compiler. Change-Id: I90fa6aa356b3e14ec25e3294b17ed10f429a9a38 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/15635 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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